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Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability

  • Pascal Benoit
  • Gilles Sassatelli
  • Lionel Torres
  • Didier Demigny
  • Michel Robert
  • Gaston Cambon
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

SoCs became reality: an increasing number of products powered by this type of circuits hits the market. Reduced power consumption, increased performance are some of the usually stated benefits. Besides approaches aiming at enabling system level exploration for multiple million gates designs, like the SystemC initiative, choosing the right IP core, or the right set of parameters among those available is not straightforward. In this article we first present a generic model for digital signal processing architectures. Several metrics, later referred as Remanence and Operative Density are presented in this paper. The methodology is illustrated through a case study.

Keywords

Global Mode Silicon Area Configuration Memory RISC Processor Configuration Layer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Pascal Benoit
    • 1
  • Gilles Sassatelli
    • 1
  • Lionel Torres
    • 1
  • Didier Demigny
    • 2
  • Michel Robert
    • 1
  • Gaston Cambon
    • 1
  1. 1.LIRMM, UMR UM2-CNRS C5506Montpellier Cedex 5France
  2. 2.ETIS, UMR-CNRS 8051Cergy Pontoise CedexFrance

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