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A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures

  • David Guevorkian
  • Petri Liuha
  • Aki Launiainen
  • Ville Lappalainen
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

A methodology for designing processor architectures oriented to matrix-vector operations is proposed in this paper. The methodology is based on high-radix multiplication where first a list of potential partial products (PPs) of one operand with all possible t-bit numbers (t∈ { 2, 3, 4 } ) are computed by simple shifts and additions, then selected PPs from this list are shifted and added according to t-bit slices of the other operand. Main advantage of the proposed method is that the list of potential PPs may be reused whenever one multiplicand is to be multiplied with several multipliers. Another advantage is that the hardware blocks involved for high-radix multiplication may also be used independently to implement other tasks such as parallel addition/subtractions, accumulations. This allows introducing a group of modifications to high-radix multiplier structures making them reconfigurable so that single devices having two-fold functionalities of either programmable processors or reconfigurable hardware accelerators may be designed.

Keywords

Pipeline Stage Multiplier Structure Hardware Accelerator Programmable Processor Register Array 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    MacSorley, O.L.: High speed arithmetic in binary computers. In: Proc. IRE, an. (1961)Google Scholar
  2. 2.
    Booth, A.D.: A signed binary multiplication technique. Quarterly J. Mechan Appl. Math. IV(2) (1951)Google Scholar
  3. 3.
    Yeh, W.-C., Jen, C.-W.: High-speed Booth encoded parallel multiplier design. IEEE Trans. on Computers 49(7), 692–701 (2000)CrossRefGoogle Scholar
  4. 4.
    Sam, H., Gupta, A.: A generalized multibit recoding of two’s complement binary numbers and its proof with applications in multiplier implementations. IEEE Trans. on Computers 39(8), 1006–1015 (1990)CrossRefGoogle Scholar
  5. 5.
    Conway, C.M., Swartzlander Jr., E.E.: Product select multiplier. In: Proceedings of the IEEE Twenty-Eighth Asilomar Conference on Signals, Systems and Computers, October-November 1994, vol. 2, pp. 1388–1392 (1994)Google Scholar
  6. 6.
    Schwarz, E.M., Averill III, R.M., Sigal, L.J.: ’A radix-8 CMOS S/390 multiplier. In: Proceedings of the 13th IEEE Symposium on Computer Arithmetic, July 1997, pp. 2–9 (1997)Google Scholar
  7. 7.
    Guevorkian, D., Launiainen, A., Liuha, P., Lappalainen, V.: Architectures for the sum of absolute differences operation. In: Proceedings, of the IEEE Worshop onc Signal Processing Systems (SIPS 2002), San Diego, California, October 2002, pp. 57–62 (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • David Guevorkian
    • 1
  • Petri Liuha
    • 1
  • Aki Launiainen
    • 1
  • Ville Lappalainen
    • 1
  1. 1.Nokia Research Center 

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