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Register-Based Permutation Networks for Stride Permutations

  • Tuomas Järvinen
  • Jarmo Takala
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

In several digital signal processing algorithms, intermediate results between computational stages are reordered according to stride permutations. If such algorithms are computed in parallel with reduced number of processing elements where one element computes several computational nodes, the permutation, instead of being hardwired, requires a storage of intermediate data elements. In this paper, register-based permutation networks for stride permutations are proposed. The proposed networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the minimum of register complexity, i.e., the number of registers, indicating area-efficiency.

Keywords

Timing Diagram Very Large Scale Integration Matrix Transpose Register Allocation Fast Fourier Trans 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Tuomas Järvinen
    • 1
  • Jarmo Takala
    • 1
  1. 1.Tampere University of TechnologyTampereFinland

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