Advertisement

An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs

  • Ulrich Heinkel
  • Claus Mayer
  • Charles Webb
  • Hans Sahm
  • Werner Haas
  • Stefan Gossens
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

This paper describes our state-of-the-art design flow used for specification, implementation and verification of a 10 million gates ASIC System-on-Chip (SoC) for a Sonet/SDH application. We present our tools and methodologies currently used and/or being developed for a multisite ASIC design project from the first specification up to the gate level netlist: our multi-site data management environment VHDLDevSys, our multi-use and re-use library ADK-Lib and our multi-platform VHDL/C++ simulation/verification environment PROVerify together with the employment of formal methods.

Keywords

Board Level Verification Strategy Library Element VHDL Code Synchronous Digital Hierarchy 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Smith, K.: A New Design Cost Model for the, ITRS, Proceedings of ISQED, IEEE 0-7695-1561-4/02 (2001)Google Scholar
  2. 2.
    Moretti: System Level Design merits a closer look, EDN , Febuary 21 (2002), http://www.edamag.com
  3. 3.
    ITU-T G.709/Y.1331: Interfaces for the optical transport network Google Scholar
  4. 4.
    ITU-T G.707/Y.1322: Network node interface for the Synchronous Digital Hierarchy (SDH) Google Scholar
  5. 5.
    Drechsler, H.: Gatecomp: Equivalence Checking of Digital Circuits in an Industrial Environment. In: International Workshop on Boolean Problems, Freiberg, pp. 195–200 (2002)Google Scholar
  6. 6.
    Haas, H., Gossens: Integration of Formal Specification into the Standard ASIC Design Flow. In: 7th IEEE/IEICE International Symposium on High Assurance Systems Engineering, Tokio (2002)Google Scholar
  7. 7.
    Heitmeyer, J., Labaw: Automated consistency checking of requirements specifications. ACM Transactions on Software Engineering and Methodology 5(3), 231–261 (1996)CrossRefGoogle Scholar
  8. 8.
    Mayer, S., Schuck, P.: VHDL Development System and Coding Standard. In: Design Automation Conference Las Vegas (1996)Google Scholar
  9. 9.
    Sahm, M., Pleickhardt, S.: OMI-326 VHDL Coding Standard. Omimo (1996)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Ulrich Heinkel
    • 1
  • Claus Mayer
    • 1
  • Charles Webb
    • 1
  • Hans Sahm
    • 1
  • Werner Haas
    • 2
  • Stefan Gossens
    • 2
  1. 1.Lucent Technologies Network Systems GmbH 
  2. 2.University of Erlangen-Nuremberg 

Personalised recommendations