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Synthesis of Asynchronous Hardware from Petri Nets

  • Josep Carmona
  • Jordi Cortadella
  • Victor Khomenko
  • Alex Yakovlev
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3098)

Abstract

As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call for new approaches in the area of behavioural models. This paper focuses on some of recent developments and new opportunities for Petri nets in designing asynchronous circuits such as synthesis of asynchronous control circuits from large Petri nets generated from front-end specifications in hardware description languages. These new methods avoid using full reachability state space for logic synthesis. They include direct mapping of Petri nets to circuits, structural methods with linear programming, and synthesis from unfolding prefixes using SAT solvers.

Keywords

Integer Linear Program Conjunctive Normal Form Integer Linear Program Model Reachability Graph Hardware Description Language 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Josep Carmona
    • 1
  • Jordi Cortadella
    • 1
  • Victor Khomenko
    • 2
  • Alex Yakovlev
    • 2
  1. 1.Universitat Politècnica de CatalunyaBarcelonaSpain
  2. 2.University of NewcastleNewcastle upon TyneUK

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