Abstract
Energy has emerged as a critical constraint in mobile computing because the power availability in most of these systems is limited by the battery power of the device. In this paper, we focus on the memory energy dissipation. This is motivated by the fact that, for data intensive applications, a significant amount of energy is dissipated in the memory. Advanced memory architectures like the Mobile SDRAM and the RDRAM support multiple power states of memory banks, which can be exploited to reduce energy dissipation in the system. Therefore, it is important to design efficient controller policies that transition among power states. Since the addressed memory chip must be in the active state in order to perform a read/write operation, the key point is the tradeoff between the energy reduction due to the use of low power modes and the energy overheads of the resulting activations. The lack of rigorous models for energy analysis is the main motivation of this work. Assuming regular transitions, we derive a formal model that captures the relation between the energy complexity and the memory activities. Given a predetermined number of activations, we approximate the optimal repartition among available power modes. We evaluate our model on the RDRAM and analyze the behavior of each parameter together with the energy that can be saved or lost.
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References
Catthoor, F., Wuytack, S., Greef, E.D., Balasa, F., Nachtergaele, L., Vandecappelle, A.: Custom memory management methodology - exploration of memory organization for embedded multimedia system design, June 1998. Kluwer Academic Pub., Dordrecht (1998)
Lebeck, A.R., Fan, X., Zeng, H., Ellis, C.S.: Power aware page allocation. In: Int. Conf. Arch. Support Prog. Lang. Ope. Syst. (November 2000)
Kamble, M.B., Ghose, K.: Analytical energy dissipation models for low power caches. In: Int. Symp. Low Power Electronics and Design (1997)
Shiue, W.-T., Chakrabarti, C.: Memory exploration for low power embedded systems. In: Proc. DAC 1999, New Orleans, Louisina (1999)
Su, C., Despain, A.: Cache design trade-offs for power and performance optimization: a case study. In: Proc. Int. Symp. on Low Power Design, pp. 63–68 (1995)
Brooks, D., Martonosi, M.: Dynamically exploiting narrow width operands to improve processor power and performance. In: Proc. Fifth Intl. Symp. High-Perf. Computer Architecture, Orlando (January 1999)
Tiwari, V., Malik, S., Wolfe, A., Lee, T.C.: Instruction Level Power Analysis and Optimization of Software. Journal of VLSI Signal Processing Systems 13(2) (August 1996)
Toburen, M.C., Conte, T.M., Reilly, M.: Instruction scheduling for low power dissipation in high performance processors. In: Proc. the Power Driven Micro-Architecture Workshop in conjunction with ISCA 1998, Barcelona (June 1998)
Ye, W., Vijaykrishnan, N., Kandemir, M., Irwin, M.J.: The design and use of SimplePower: a cycle-accurate energy estimation tool. In: Proc. Design. Automation Conference (DAC), Los Angeles, June 5-9 (2000)
Austin, T.: Simplescalar, Master’s thesis, University of Wisconsin (1998)
128/144-MBit Direct RDRAM Data Sheet, Rambus Inc. (May 1999)
Delaluz, V., Kandemir, M., Vijaykrishnan, N., Sivasubramaniam, A., Irwin, M.: Memory energy management using software and hardware directed power mode control. Tech. Report CSE-00-004, The Pennsylvania State University (April 2000)
Wolf, W.: Software-Hardware Codesign of Embedded Systems. Proceedings of the IEEE 82 (1998)
Ernst, R.: Codesign of Embedded Systems: Status and Trends. IEEE Design and Test of Computers 15 (1998)
Schlett, M.: Trends in Embedded Microprocessors Design. IEEE Computer (1998)
Mobile SDRAM Power Saving Features, Technical Note TN-48-10, MICRON, http://www.micron.com
Tang, W., Veidenbaum, A.V., Gupta, R.: Architectural Adaptation for Power and Performance. In: International Conference on ASIC (2001)
Bebini, L., De Micheli, G.: Sytem-Level Optimization: Techniques and Tools. ACM Transaction on Design Automation of Electronic Systems (2000)
Okuma, T., Ishihara, T., Yasuura, H.: Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Design and Test of Computers (2001)
Pouwelse, J., Langendoen, K., Sips, H.: Dynamic Voltage Scaling on a Low- Power Microprocessor. UbiCom-Tech. Report (2000)
Singh, M., Prasanna, V.K.: Algorithmic Techniques for Memory Energy Reduction. In: Worshop on Experimental Algorithms, Ascona, Switzerland, May 26-28 (2003)
Sen, S., Chatterjee, S.: Towards a Theory of Cache-Efficient Algorithms. In: SODA (2000)
Tadonki, C., Rolim, J., Singh, M., Prasanna, V.: Combinatorial Techniques for Memory Power State Scheduling in Energy Constrained Systems. In: Solis-Oba, R., Jansen, K. (eds.) WAOA 2003. LNCS, vol. 2909, pp. 265–268. Springer, Heidelberg (2004)
Bacon, D.F., Graham, S.L., Sharp, O.J.: Compiler Transformations for High-Performance Computing. Hermes (1994)
Fan, X., Ellis, C.S., Lebeck, A.R.: Memory Controller Policies for DRAM Power Management. In: ISLPED 2001, Huntington Beach, California, August 6-7 (2001)
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Tadonki, C., Rolim, J. (2004). An Analytical Model for Energy Minimization. In: Ribeiro, C.C., Martins, S.L. (eds) Experimental and Efficient Algorithms. WEA 2004. Lecture Notes in Computer Science, vol 3059. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24838-5_41
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DOI: https://doi.org/10.1007/978-3-540-24838-5_41
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