Abstract
In this paper, an efficient non-scan DFT(Design For Testability) method described in RTL for datapath is proposed. The proposed non-scan DFT method improves testability of datapath based on hierarchical testability analysis regardless of the datapath width. It always guarantees higher fault efficiency and little hardware overhead than previous methods. The experimental results show that the proposed method has superior abilities of test application time and area overhead compared to the scan method.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Ohtake, S., Wada, H., Masuzawa, T., Fujiwara, H.: A Non-Scan DFT Method at Register- Transfer Level to Achieve Complete Fault Efficiency. In: Asian South Pacific Design Automation Conference (2000)
Maxwell, P.C., Aitken, R.C., Johnson, V., Chiang, I.: The effect of different test sets on quality level prediction: When is 80% better than 90%?. In: International Test Conference (1991)
Mhattacharya, S., Brglez, F., Dey, S.: Transformations and resynthesis for testability of RTlevel control-data path specifications. IEEE Transaction on VLSI System (1993)
Dey, S., Potkonjak, M.: Non-scan design-for-testability of RT-level data paths. In: International Conference on Computer-Aided Design (1994)
Dey, S., Gangaram, V., Potkonjak, M.: A controller-based design-for-testability technique for controller-data path circuits. In: International Conference on Computer-Aided Design (1995)
Ghosh, I., Raghunathan, A., Jha, N.K.: Design for Hierarchical Testability of RTL Circuits Obtained by Behavioral Synthesis. In: International Conference on Computer-Aided Design (1995)
Bhatia, S., Jha, N.K.: Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches. In: International Conference on Computer Design (1994)
Ghosh, I., Jha, N.K., Bhawmik, S.: A BIST Scheme for RTL Circuits Based on Symbolic Testability Analysis. IEEE Transaction on Computer-Aided Design of Integrated Circuits and System (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Yang, S., Kim, M., Park, J., Chang, H. (2004). A Study on Methodology for Enhancing Reliability of Datapath. In: Laganá, A., Gavrilova, M.L., Kumar, V., Mun, Y., Tan, C.J.K., Gervasi, O. (eds) Computational Science and Its Applications – ICCSA 2004. ICCSA 2004. Lecture Notes in Computer Science, vol 3043. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24707-4_10
Download citation
DOI: https://doi.org/10.1007/978-3-540-24707-4_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22054-1
Online ISBN: 978-3-540-24707-4
eBook Packages: Springer Book Archive