Abstract
Recently efficient implementation of finite field operations has received a lot of attention. Among GF(2m) arithmetic operations, a multiplication process is the most basic and a critical operation that determines a speed-up in hardware. Mastrovito multipliers using a trinomial p(x)=x m+x n+1(n≠ m/2) require m 2-1 XOR gates and m 2 AND gates. The proposed multiplier that depends on the intermediate term x n needs m 2 AND gates and m 2+(n 2-3n)/2 XOR gates. The time complexity of existing multipliers is T A +([(m-2)/(m-n)] + 1+ [log 2 m ]) T X and that of the proposed method is T A +(1+[ log 2 (m-1 + [ n/2 ]) ]) T X . The proposed architecture is efficient for the extension degree m suggested as standards: SEC2, ANSI X9.63. In average, the space complexity is increased to 1.18% but the time complexity is reduced 9.036%.
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Lee, S.O., Jung, S.W., Kim, C.H., Yoon, J., Koh, JY., Kim, D. (2004). Design of Bit Parallel Multiplier with Lower Time Complexity. In: Lim, JI., Lee, DH. (eds) Information Security and Cryptology - ICISC 2003. ICISC 2003. Lecture Notes in Computer Science, vol 2971. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24691-6_11
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DOI: https://doi.org/10.1007/978-3-540-24691-6_11
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