Abstract
The configurable microprocessor array for DSP applications is proposed, in which each cell is the microprocessor with RISC architecture, represented as a soft IP-core. This IP-core is generated automatically by the special soft-core generator, which is based on the approach to optimization of a microprocessor architecture for its further implementation in FPGA devices. Soft-core generator analyzes the executing program of each microprocessor of the array and eliminates all unused units from the resulting VHDL-model of the microprocessor. Therefore, hardware volume of each cell of this array is minimized, and is adapted to the used instruction subset. The soft-core generator provides both high throughput and minimized hardware volume with speedups the design process. It was probed in design the microprocessor array for solving the linear equation system with Toeplitz matrices.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Villasenor, J., Hutchings, B.: The flexibility of configurable computing. IEEE Signal Processing Magazine 15, 67–84 (1998)
Sergyienko, A., Maslennikov, O.: Implementation of Givens QR Decomposition in FPGA. In: Wyrzykowski, R., Dongarra, J., Paprzycki, M., Waśniewski, J. (eds.) PPAM 2001. LNCS, vol. 2328, pp. 453–459. Springer, Heidelberg (2002)
Lepekha, V., Sergyienko, A., Kaniewski, J.: VHDL-Model of Ultrafast Microcontroller 8051. In: Proc. 3-d Region. Conf. Reprogramowalne Uklady Cyfrowe, RUC 2000, Poland, pp. 35–41 (2000)
Maslennikov, O.: Configurable microcontroller array. In: Proc. of the 3-d Int. Conf. on Parallel Computing in Electrical Engineering, PARELEC 2002, Warszaw, Poland, pp. 47–49 (2002)
Sergyienko, A.: VHDL for computer development. Kiev, Diasoft (2003) (in Russian)
Sergyienko, A., Kaniewski, J., Maslennikov, O., Wyrzykowski, R.: Mapping regular algorithms into processor arrays using software pipelining. In: Proc. of the 1-st Int. Conf. on Parallel Computing in Electrical Engineering, PARELEC 1998, Poland, pp. 197–200 (1998)
Kanevski, J.S., Sergienko, A., Piech, H.: A Method for the Structural Synthesis of Pipelined Array Processors. In: Proc. of the 1-st Int. Conf. on Parallel Proc. and Appl. Math., PRAM 1994, Poland, pp. 100–109 (1994)
Kung, S.Y.: VLSI processor arrays. Prentice Hall, Englewood Cliffs (1988)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Maslennikow, O., Shevtshenko, J., Sergyienko, A. (2004). Configurable Microprocessor Array for DSP Applications. In: Wyrzykowski, R., Dongarra, J., Paprzycki, M., Waśniewski, J. (eds) Parallel Processing and Applied Mathematics. PPAM 2003. Lecture Notes in Computer Science, vol 3019. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24669-5_5
Download citation
DOI: https://doi.org/10.1007/978-3-540-24669-5_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-21946-0
Online ISBN: 978-3-540-24669-5
eBook Packages: Springer Book Archive