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FV-MSB: A Scheme for Reducing Transition Activity on Data Buses

  • Dinesh C. Suresh
  • Jun Yang
  • Chuanjun Zhang
  • Banit Agrawal
  • Walid Najjar
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2913)

Abstract

Power consumption becomes an important issue for modern processors. The off-chip buses consume considerable amount of total power [9,7]. One effective way to reduce power is to reduce the overall bus switching activities since they are proportional to the power. Up till now, the most effective technique in reducing the switching activities on the data buses is Frequent Value Encoding (FVE) that exploits abundant frequent value locality on the off-chip data buses. In this paper, we propose a technique that exploits more value locality that was overlooked by the FVE. We found that a significant amount of non-frequent values, not captured by the FVE, share common high-ordered bits. Therefore, we propose to extend the current FVE scheme to take bit-wise frequent values into consideration. On average, our technique reduces 48% switching activity. The average energy saving we achieved is 44.8%, which is 8% better than the FVE.

Keywords

Switching Activity Very Large Scale Integration Normal Program Content Addressable Memory Average Energy Saving 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Basu, K., Choudhary, Q., Pisharath, J., Kandemir, M.: Power Protocol: Reducing Power dissipation on off-chip Data Buses. In: The 35th IEEE/ACM International symposium on Microarchitecture, pp. 345–355 (2002)Google Scholar
  2. 2.
    Benini, L., Macii, A., Macii, E., Poncino, M., Scarsi, R.: Synthesis of Low-Overhead Interfaces for Power-Efficient Communication Over Wide Buses. In: ACM/IEEE Design Automation Conference, pp. 128–133 (1999)Google Scholar
  3. 3.
    Cadence Corporation: http://www.cadence.com
  4. 4.
    Burger, D., Austin, T.: The SimpleScalar Tool Set, Version 2.0., Technical Report 1342, Universoty of Wisconsin-Madison, Computer science Department (1997)Google Scholar
  5. 5.
    Messmer, H.: The Indispensable PC Hardware Book, 4th edn. Addison-Wesley, Reading (2002)Google Scholar
  6. 6.
    The Mosis Service: http://www.mosis.com/
  7. 7.
    Stan, M.R., Burleson, W.P.: Bus-invert coding for low-power I/O. IEEE Transactions on very Large Scale Integration (VLSI) systems 3, 49–58 (1995)CrossRefGoogle Scholar
  8. 8.
    Yang, J., Gupta, R.: FV Encoding for Low-Power Data I/O. In: ACM/IEEE International Symposium on Low Power Electronic Design, pp. 84–87 (2001)Google Scholar
  9. 9.
    Zhang, Y., Yang, J., Gupta, R.: Frequent Value Locality and Value-centric Data Cache Design. In: The Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS IX), pp. 150–159 (2000)Google Scholar
  10. 10.
    Efthymiou, A., Garside, J.D.: An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks. In: Proceedings of the International Symposium On Low Power Electronics and Design (2002)Google Scholar
  11. 11.
    Citron, D., Rudolph, L.: Creating a wider bus using caching techniques. In: Proceedings of the first International symposium on High Performance Computer Architecture, January 1995, pp. 90–99 (1995)Google Scholar
  12. 12.
    Farrens, M., Park, A.: Dynamic base register caching: A technique for reducing address bus width. In: Proceedings of 18th Annual International Symposium on Computer Architecture, Toronto, Canada, May 1991, pp. 128–137 (1991)Google Scholar
  13. 13.
    Musoll, E., Lang, T., Cortadella, J.: Working-zone encoding for reducing the energy in microprocessor address buses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6 (1998)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Dinesh C. Suresh
    • 1
  • Jun Yang
    • 1
  • Chuanjun Zhang
    • 2
  • Banit Agrawal
    • 1
  • Walid Najjar
    • 1
  1. 1.Computer Science and Engineering DepartmentUniversity of CaliforniaRiversideUSA
  2. 2.Electrical Engineering DepartmentUniversity of CaliforniaRiversideUSA

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