Abstract
In this paper, we present a novel technique to reduce dynamic and static power dissipation in the issue queue. The proposed scheme is based on delaying the dispatch of instructions whenever this delay is expected not to degrade performance. The proposed technique outperforms previous schemes in both performance and power savings. It achieves more than 34% dynamic and 21% static power savings in the issue queue at the expense of just 1.77% IPC loss. Significant power savings may be also achieved for the register file.
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Abella, J., González, A. (2003). Power-Aware Adaptive Issue Queue and Register File. In: Pinkston, T.M., Prasanna, V.K. (eds) High Performance Computing - HiPC 2003. HiPC 2003. Lecture Notes in Computer Science, vol 2913. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24596-4_5
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DOI: https://doi.org/10.1007/978-3-540-24596-4_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20626-2
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