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Power-Aware Adaptive Issue Queue and Register File

  • Jaume Abella
  • Antonio González
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2913)

Abstract

In this paper, we present a novel technique to reduce dynamic and static power dissipation in the issue queue. The proposed scheme is based on delaying the dispatch of instructions whenever this delay is expected not to degrade performance. The proposed technique outperforms previous schemes in both performance and power savings. It achieves more than 34% dynamic and 21% static power savings in the issue queue at the expense of just 1.77% IPC loss. Significant power savings may be also achieved for the register file.

Keywords

Interval Length Power Saving Register File Superscalar Processor Reorder Buffer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Jaume Abella
    • 1
  • Antonio González
    • 1
    • 2
  1. 1.Computer Architecture DepartmentU. Politècnica CatalunyaBarcelonaSpain
  2. 2.Intel Barcelona Research Center, Intel LabsU. Politècnica CatalunyaBarcelonaSpain

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