Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors
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Although many performance studies of memory speculation mechanisms in speculative multithreading chip multiprocessors have been reported, it is still unclear whether the mechanisms are complexity effective and worth implementing. In this paper, we perform a complexity analysis of a cache controller designed by extending an MSI controller to support thread-level memory speculation. We model and estimate the delay of the control logic on critical paths and the area overhead to hold additional control bits in the cache directory. Our analysis shows that for many protocol operations, the directory access time occupies more than half of the total delay. The total overhead is however smaller than the delay for accessing the cache tags. Since the protocol operations can be performed in parallel with the tag access, the resulting critical path latency is only slightly increased.
KeywordsCritical Path Total Delay Protocol Operation Thread Level Parallelism Speculative Thread
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