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Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors

  • Yoshimitsu Yanagawa
  • Luong Dinh Hung
  • Chitaka Iwama
  • Niko Demus Barli
  • Shuichi Sakai
  • Hidehiko Tanaka
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2913)

Abstract

Although many performance studies of memory speculation mechanisms in speculative multithreading chip multiprocessors have been reported, it is still unclear whether the mechanisms are complexity effective and worth implementing. In this paper, we perform a complexity analysis of a cache controller designed by extending an MSI controller to support thread-level memory speculation. We model and estimate the delay of the control logic on critical paths and the area overhead to hold additional control bits in the cache directory. Our analysis shows that for many protocol operations, the directory access time occupies more than half of the total delay. The total overhead is however smaller than the delay for accessing the cache tags. Since the protocol operations can be performed in parallel with the tag access, the resulting critical path latency is only slightly increased.

Keywords

Critical Path Total Delay Protocol Operation Thread Level Parallelism Speculative Thread 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Yoshimitsu Yanagawa
    • 1
  • Luong Dinh Hung
    • 2
  • Chitaka Iwama
    • 2
  • Niko Demus Barli
    • 2
  • Shuichi Sakai
    • 2
  • Hidehiko Tanaka
    • 2
  1. 1.The Institute of Space and Astronautical ScienceKanagawaJapan
  2. 2.Graduate School of Information Science and TechnologyThe University of TokyoTokyoJapan

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