An Efficient Algorithm to Compute Delay Set in SPMD Programs
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We present compiler analysis for single program multiple data (SPMD) programs that communicate through shared address space. The choice of memory consistency model is sequential consistency as defined by Lamport . Previous research has shown that these programs require cycle detection to perform any kind of code re-ordering either at hardware or software. So far, the best known cycle detection algorithm for SPMD programs has been given by Krishnamurthy et al [5, 6, 8]. Their algorithm computes a delay set that is composed of those memory access pairs that if re-ordered either by hardware or software may cause violation of sequential consistency. This delay set is computed in O(m 3) time where m is the number of read/write accesses. In this paper, we present O(m 2) algorithm for computing analogous delay set for SPMD programs that are used in practice. These programs must be structured with the property that all the variables are initialized before their value is read.
KeywordsMemory Access Critical Section Program Variable Sequential Consistency Cycle Detection
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