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Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification

  • B. Jayaram
  • A. Manoj Kumar
  • V. Kamakoti
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2913)

Abstract

Redundancy identification is a challenging open problem in logic optimization of Boolean circuits. Partitioning techniques are employed successfully to solve the redundancy identification problem with less time and higher scalability. Any heuristic/algorithm for the Logic optimization problem, and hence the redundancy identification problem is compute-intensive, especially when very high approximation to the optimal solution is demanded. This is because the problems are NP-complete. This necessitates parallel heuristics/algorithms to speed-up the computation process. In this paper, we present a parallel partitioning approach for the logic optimization problem using the concept of redundancy identification. This result finds extensive applications in the area of VLSI CAD tool design.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • B. Jayaram
    • 1
  • A. Manoj Kumar
    • 1
  • V. Kamakoti
    • 1
  1. 1.Indian Institute of Technology 

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