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Graphen Algorithmen Netze pp 388–442Cite as

Einige graphentheoretische Aspekte des VLSI-Layout

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Part of the book series: Moderne Kommunikationstechnik ((XMK))

Zusammenfassung

Für die Implementierung logischer Funktionen mit mehreren Ausgängen haben sich Programmierbare Logikfelder als ein effektives Mittel erwiesen. Im Englischen spricht man von Programmable Logic Arrays — von dort wollen wir für das Weitere die Abkürzung PLA übernehmen.

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Literatur

  1. Garey, M.R.; Johnson, D.S. Computers and intractability W.H. Freeman, 1979

    MATH  Google Scholar 

  2. Golumbic, M.C. Algorithmic graph theory and perfect graphs Academic Press, 1980

    MATH  Google Scholar 

  3. Hachtel, G.D.; Newton, A.R.; Sangiovanni — Vincentelli, A.L. An Algorithm for Optimal PLA Folding IEEE Trans. CAD of Int. Circuits and Systems (1982) 63–77

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  4. Hu, T.C.; Kuo, Y.S. Graph Folding and Programmable Logic Array Networks 17 (1987) 19–37

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  5. Kashiwabara, T.; Fujisawa, T. NP-completeness of the problem of finding a minimum-clique-number interval graph containing a given graph as a subgraph Proc. 1979 Intern. Symp. on Circuits and Systems, pp. 657–660

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  6. Kirousis, L.M.; Papadimitriou, C.H. Searching and pebbling Theoret. Comp. Science 47 (1986), 205–218

    Article  MathSciNet  MATH  Google Scholar 

  7. Lengauer, T. Combinatorial algorithms for integrated circuit layout Wiley, 1990

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  8. Möhring, R.H. Graph problems related to gate matrix layout and PLA folding in: G. Timhofer et al. (eds.), Computational Graph Theory, Computing Supplement 7, Springer Verlag Wien, 1990, p. 16–51

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Authors
  1. Firoz Kaderali
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  2. Werner Poguntke
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© 1995 Friedr. Vieweg & Sohn Verlagsgesellschaft mbH, Braunschweig/Wiesbaden

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Kaderali, F., Poguntke, W. (1995). Einige graphentheoretische Aspekte des VLSI-Layout. In: Graphen Algorithmen Netze. Moderne Kommunikationstechnik. Vieweg+Teubner Verlag. https://doi.org/10.1007/978-3-322-89870-8_10

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  • DOI: https://doi.org/10.1007/978-3-322-89870-8_10

  • Publisher Name: Vieweg+Teubner Verlag

  • Print ISBN: 978-3-528-06662-8

  • Online ISBN: 978-3-322-89870-8

  • eBook Packages: Springer Book Archive

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