Advertisement

SIMD Acceleration for Main-Memory Index Structures – A Survey

  • Marten Wallewein-Eising
  • David BroneskeEmail author
  • Gunter Saake
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 928)

Abstract

Index structures designed for disk-based database systems do not fulfill the requirements for modern database systems. To improve the performance of these index structures, different approaches are presented by several authors, including horizontal vectorization with SIMD and efficient cache-line usage.

In this work, we compare the adapted index structures Seg-Tree/Trie, FAST, VAST, and ART and evaluate the usage of SIMD within these. We extract important criteria of these adaptations and weight them according to their impact on the performance. As a result, we infer adaptations that are promising for our own index structure Elf.

Notes

Acknowledgments

We thank all reviewers for their constructive feedback. This work was partially funded by the DFG (grant no.: SA 465/50-1).

References

  1. 1.
    Bender, M.A., Demaine, E.D., Farach-Colton, M.: Cache-oblivious B-trees. In: Proceedings of the Annual Symposium on Foundations of Computer Science, pp. 399–409. IEEE (2000)Google Scholar
  2. 2.
    Bender, M.A., Farach-Colton, M., Kuszmaul, B.C.: Cache-oblivious string B-trees. In: Proceedings of the Symposium on Principles of Database Systems (PODS), pp. 233–242. ACM (2006)Google Scholar
  3. 3.
    Borodin, A., Mirvoda, S., Kulikov, I., Porshnev, S.: Optimization of memory operations in generalized search trees of PostgreSQL. In: Kozielski, S., Mrozek, D., Kasprowski, P., Małysiak-Mrozek, B., Kostrzewa, D. (eds.) BDAS 2017. CCIS, vol. 716, pp. 224–232. Springer, Cham (2017).  https://doi.org/10.1007/978-3-319-58274-0_19CrossRefGoogle Scholar
  4. 4.
    Broneske, D., Breß, S., Heimel, M., Saake, G.: Toward hardware-sensitive database operations. In: Proceedings of the International Conference on Extending Database Technology (EDBT), pp. 229–234 (2014)Google Scholar
  5. 5.
    Broneske, D., Breß, S., Saake, G.: Database scan variants on modern CPUs: a performance study. In: Jagatheesan, A., Levandoski, J., Neumann, T., Pavlo, A. (eds.) IMDM 2013-2014. LNCS, vol. 8921, pp. 97–111. Springer, Cham (2015).  https://doi.org/10.1007/978-3-319-13960-9_8CrossRefGoogle Scholar
  6. 6.
    Broneske, D., Köppen, V., Saake, G., Schäler, M.: Accelerating multi-column selection predicates in main-memory - the Elf approach. In: Proceedings of the International Conference on Data Engineering (ICDE), pp. 647–658. IEEE (2017)Google Scholar
  7. 7.
    Broneske, D., Saake, G.: Exploiting capabilities of modern processors in data intensive applications. IT - Inf. Technol. 59(3), 133–140 (2017).  https://doi.org/10.1515/itit-2016-0049CrossRefGoogle Scholar
  8. 8.
    Graefe, G., Larson, P.A.: B-tree indexes and CPU caches. In: Proceedings of the International Conference on Data Engineering (ICDE), pp. 349–358. IEEE (2001)Google Scholar
  9. 9.
    Kim, C., et al.: FAST: fast architecture sensitive tree search on modern CPUs and GPUs. In: Proceedings of the International Conference on Management of Data (SIGMOD), pp. 339–350. ACM (2010)Google Scholar
  10. 10.
    Leis, V., Kemper, A., Neumann, T.: The adaptive radix tree: ARTful indexing for main-memory databases. In: Proceedings of the International Conference on Data Engineering (ICDE), pp. 38–49. IEEE (2013)Google Scholar
  11. 11.
    Polychroniou, O., Raghavan, A., Ross, K.A.: Rethinking SIMD vectorization for in-memory databases. In: Proceedings of the International Conference on Management of Data (SIGMOD), pp. 1493–1508. ACM (2015)Google Scholar
  12. 12.
    Rao, J., Ross, K.A.: Cache conscious indexing for decision-support in main memory. In: Proceedings of the International Conference on Very Large Databases (VLDB), vol. 99, pp. 78–89 (1999)Google Scholar
  13. 13.
    Rao, J., Ross, K.A.: Making B+-trees cache conscious in main memory. In: ACM SIGMOD Record, vol. 29, pp. 475–486. ACM (2000)Google Scholar
  14. 14.
    Schlegel, B., Gemulla, R., Lehner, W.: K-ary search on modern processors. In: Proceedings of the International Workshop on Data Management on New Hardware (DaMoN), pp. 52–60. ACM (2009)Google Scholar
  15. 15.
    Suaib, M., Palaty, A., Pandey, K.S.: Architecture of SIMD type vector processor. Int. J. Comput. Appl. 20(4) (2011)Google Scholar
  16. 16.
    Yamamuro, T., Onizuka, M., Hitaka, T., Yamamuro, M.: VAST-Tree: a vector-advanced and compressed structure for massive data tree traversal. In: Proceedings of the International Conference on Extending Database Technology (EDBT), pp. 396–407. ACM (2012)Google Scholar
  17. 17.
    Zeuch, S., Huber, F., Freytag, J.: Adapting tree structures for processing with SIMD instructions. In: Proceedings of the International Conference on Extending Database Technology (EDBT). Citeseer (2014)Google Scholar
  18. 18.
    Zukowski, M., Heman, S., Nes, N., Boncz, P.: Super-scalar RAM-CPU cache compression. In: Proceedings of the International Conference on Data Engineering (ICDE), p. 59. IEEE (2006)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2018

Authors and Affiliations

  • Marten Wallewein-Eising
    • 1
  • David Broneske
    • 1
    Email author
  • Gunter Saake
    • 1
  1. 1.University of MagdeburgMagdeburgGermany

Personalised recommendations