Abstract
We present a circuit design for garbage-free reversible multiplier. Given inputs \(A,\,B\) and R, where \(0\le B < 2^m\) and \(0\le R<A<2^n\), the circuit outputs A and \(P = A\cdot B+R\). Applied in reverse, the circuit takes as input A and P, where \(0<A<2^n\) and \(0\le P< 2^mA\), and outputs A, \(B = P/A\) and \(R = P\%A\). The circuit uses a total of two ancilla bits.
The circuit is constructed as a sequence of m modified ripple-carry adders and comparators, both of which have O(n) gate delay, so the multiplier has O(\(m\times n\)) gate delay, but this can be improved to O(\(m\times \log (n)\)) by using a modified carry-lookahead adder and an O(\(\log (n)\)) comparator, both of which are described in the paper. The cost of reducing the gate delay to O(\(m\times \log (n)\)) is O(n) added ancilla bits and a larger gate count.
This work was partially supported by the European COST Action IC 1405: Reversible Computation - Extending Horizons of Computing.
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References
Banerjee, A., Pathak, A.: An analysis of reversible multiplier circuits. arXiv.org (2009)
Draper, T.G., Kutin, S.A., Rains, E.M., Svore, K.M.: A logarithmic-depth quantum carry-lookahead adder. Quantum Inf. Comput. 6(4), 351–369 (2006)
Jayashree, H.V., Thapliyal, H., Arabnia, H.R., Agrawal, V.K.: Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier. J. Supercomput. 72(4), 1477–1493 (2016)
Kaur, M., Singh, H., Goel, C.: Reversible multiplier-a review. Int. J. Adv. Res. Electr. Electron. Instr. Eng. 3(10) (2014)
Mogensen, T.Æ.: Garbage-free reversible constant multipliers for arbitrary integers. In: Dueck, G.W., Miller, D.M. (eds.) RC 2013. LNCS, vol. 7948, pp. 70–83. Springer, Heidelberg (2013). https://doi.org/10.1007/978-3-642-38986-3_7
Paterson, M.S., Pippenger, N., Zwick, U.: Faster circuits and shorter formulae for multiple addition, multiplication and symmetric Boolean functions. In: 31st Annual Symposium on Foundations of Computer Science, vol. 2, pp. 642–650, October 1990
Reif, J.H., Tate, S.R.: Optimal size integer division circuits. In: Proceedings of the Twenty-First Annual ACM Symposium on Theory of Computing, STOC 1989, pp. 264–273. ACM, New York (1989)
Thomsen, M.K., Axelsen, H.B., Glück, R.: A reversible processor architecture and its reversible logic design. In: De Vos, A., Wille, R. (eds.) RC 2011. LNCS, vol. 7165, pp. 30–42. Springer, Heidelberg (2012). https://doi.org/10.1007/978-3-642-29517-1_3
Van Rentergem, Y., De Vos, A.: Optimal design of a reversible full adder. Int. J. Unconv. Comput. 1, 339–355 (2005)
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Mogensen, T.Æ. (2018). Garbage-Free Reversible Multiplication and Division. In: Kari, J., Ulidowski, I. (eds) Reversible Computation. RC 2018. Lecture Notes in Computer Science(), vol 11106. Springer, Cham. https://doi.org/10.1007/978-3-319-99498-7_18
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DOI: https://doi.org/10.1007/978-3-319-99498-7_18
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