Abstract
The paper presents a BDD-based post-synthesis technique to detect the redundant gates in a reversible circuit. Given a reversible circuit C, we are looking for a maximal (or most costly) subset of gates in C that can be removed from C without altering the functionality of the circuit. The runtime of the new algorithm is linear in the size of the involved binary decision diagrams (BDD). In order to lower the runtimes, the presented approach is extended to handle the restricted problem of only looking for up to k gates that can be removed from C for some constant k. This restriction should ensure that the sizes of the involved BDDs remain practicable for adequate constants k.
Keywords
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsNotes
- 1.
The results presented in this paper have been worked out in the master thesis [13] of the first author who has been supervised by the second and third author.
- 2.
For a formal definition, please see Sect. 3.
- 3.
We can apply any cost metric in which the costs of a reversible circuit are given by the sum of the costs of the single reversible gates contained in it. For the sake of simplicity, in this paper we take the size of the redundant gate combination as cost metric.
- 4.
Remember that in this paper we defined global optimization problem as the problem of finding the most costly redundant gate combination of a given reversible circuit. In general, this will not lead to an optimal reversible circuit of the respective reversible Boolean function.
- 5.
The remaining 128 circuits could not be checked because of too high requirements for computing time or out of main memory.
References
Abdessaied, N., Drechsler, R.: Reversible and Quantum Circuits. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-31937-7
Bryant, R.E.: Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. C–35(8), 677–691 (1986)
Drechsler, R., Becker, B.: Binary Decision Diagrams - Theory and Implementaion. Kluwer Academic Publishers, Boston (1998)
Iwama, K., Kambayashi, Y., Yamashita, S.: Transformation rules for designing CNOT-based quantum circuits. In: Design Automation Conference, New Orleans, USA, pp. 419–424, June 2002
Feinstein, D.Y., Thornton, M.A., Miller, D.M.: Partially redundant logic detection using symbolice quivalence checking in reversible and irreversible logic circuits. In: Design, Automation and Test in Europe, pp. 1378–1381 (2008)
Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5(3), 183–191 (1961)
Limaye, C.A.: Formal verification techniques for reversible circuits. Master thesis, Virginia Polytechnic Institute and State University, Virginia, USA (2013)
Maslov, D., Dueck, G., Miller, D.: Toffoli network synthesis with templates. IEEE Trans. Comput. Aided Des. CAD 24(6), 807–817 (2005)
Maslov, D.: Reversible Logic Synthesis Benchmarks Page. http://webhome.cs.uvic.ca/~dmaslov
Miller, D.M., Maslov, D., Dueck, G.W.: A transformation based algorithm for reversible logic synthesis. In: Design Automation Conference, Anaheim, USA, pp. 318–323, June 2003
Miller, D.M., Thornton, M.A.: QMDD: a decision diagram structure for reversible and quantum circuits. In: 36th International Symposium on Multivalued Logic, p. 30 (2006)
Nielsen, M., Chuang, I.: Quantum Computation and Quantum Information. Cambridge University Press, Cambridge (2000)
Pfuhl, M.: Finding the redundant gates in reversible circuits. Master thesis, Institute for Computer Science, Martin Luther University Halle-Wittenberg, Germany (2018)
Prasad, A.K., Shende, V.V., Markov, I.L., Hayes, J.P., Patel, K.N.: Data structures and algorithms for simplifying reversible circuits. ACM J. Emerg. Technol. Comput. Syst. 2(4), 277–293 (2006)
Saeedi, M., Wille, R., Drechsler, R.: Synthesis of quantum circuits for linear nearest neighbor architectures. Quantum Inf. Process. 10(3), 355–377 (2011)
Saeedi, M., Markov, I.L.: Synthesis and optimization of reversible circuits - a survey. ACM Comput. Surv. 45(2) (2013). Article No. 21
Smith, A., Veneris, A.G., Ali, M.F., Viglas, A.: Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Trans. Comput. Aid. Des. CAD 24(10), 1606–1621 (2005)
Somenzi, F.: CUDD: CU Decision Diagram package, Release 3.0.0. Department of Electrical, Computer and Energy Engineering University of Colorado at Boulder, 31 December 2015. http://vlsi.colorado.edu/~fabio/CUDD/cudd_8h.html
Toffoli, T.: Reversible computing. In: de Bakker, J., van Leeuwen, J. (eds.) ICALP 1980. LNCS, vol. 85, pp. 632–644. Springer, Heidelberg (1980). https://doi.org/10.1007/3-540-10003-2_104
Wille, R., Große, D., Frehse, S., Dueck, G.W., Drechsler, R.: Debugging reversible circuits. Integration VLSI J. 44, 51–61 (2011)
Wille, R., Große, D., Teuber, L., Dueck, G.W., Drechsler, R.: RevLib: an online ressource for reversible functions and circuits. In: International Symposium on Multi-Valued Logic, pp. 220–225, Dallas, USA (2008). RevLib http://revlib.org/
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer Nature Switzerland AG
About this paper
Cite this paper
Pfuhl, M., Ritter, J., Molitor, P. (2018). Finding the Redundant Gates in Reversible Circuits. In: Kari, J., Ulidowski, I. (eds) Reversible Computation. RC 2018. Lecture Notes in Computer Science(), vol 11106. Springer, Cham. https://doi.org/10.1007/978-3-319-99498-7_14
Download citation
DOI: https://doi.org/10.1007/978-3-319-99498-7_14
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-99497-0
Online ISBN: 978-3-319-99498-7
eBook Packages: Computer ScienceComputer Science (R0)