Abstract
Multipliers are an integral block of a wide range of error-resilient applications like audio, image, and video processing, and machine learning. However, these multiplier architectures are computationally complex, and hence consume more power and occupy more area with long carry-adder trees when implementing multipliers with high bit-width. Approximate computing is an emerging design paradigm and is currently exploited to alleviate such area and power overheads, with slight/affordable degradation in the output quality of error-resilient application. An approximate multiplier architecture could either be approximated at the partial-product generation, accumulation, or summation stages. In this chapter, we focus on the different design aspects of energy-efficient approximate multipliers for both ASICs- and FPGAs-based systems.
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The Neural Network which won the ImageNet Large-Scale Visual Recognition Competition (ILSVRC) in the year 2015 to surpass human accuracy in classifying images of the image-net dataset [30].
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Rehman, S., Prabakaran, B.S., El-Harouni, W., Shafique, M., Henkel, J. (2019). Heterogeneous Approximate Multipliers: Architectures and Design Methodologies. In: Reda, S., Shafique, M. (eds) Approximate Circuits. Springer, Cham. https://doi.org/10.1007/978-3-319-99322-5_3
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