Abstract
Adders, being one of the fundamental operators in many processing applications, have received a significant amount of attention in approximate computing. Using approximate low-power and low-latency adders can have a significant effect on improving the energy efficiency and performance of a system, at the cost of reasonable accuracy loss. For this chapter, we restrict our focus towards generic configurable models for high-performance (low-latency) approximate adders. These models provide design time support for choosing appropriate low-latency approximate adder design, which offers desired level of quality while providing optimal performance. In this chapter, we also cover the mathematical analysis which shows that, provided a latency constraint, an adder configuration with the highest quality and lowest area/power requirement can effortlessly be selected from the complete design space of low-latency adders. Towards the end of the chapter, we present extensive results in support of the presented mathematical analysis and show that the selected optimal configurations indeed provide optimal results even in real-world applications.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Venkataramani S, Chakradhar ST, Roy K et al (2015) Approximate computing and the quest for computing efficiency. In: 2015 52nd ACM/EDAC/IEEE design automation conference (DAC), pp 1–6
Shafique M, Hafiz R, Rehman S et al (2016) Cross-layer approximate computing: from logic to architectures. In: Proceedings of 53rd IEEE/ACM design automation conference
Xu Q, Kim NS, Mytkowicz T (2016) Approximate computing: a survey. IEEE Des Test 33(1):8–22
Mittal S (2016) A survey of techniques for approximate computing. ACM Comput Surv 48(4):62:1–62:33
Zhu N, Goh WL, Yeo KS (2009) An enhanced low-power high-speed adder for error-tolerant application. In: Proceedings of 12th international symposium integrated circuits, pp 69–72
Verma AK, Brisk P, Ienne P (2008) Variable latency speculative addition: a new paradigm for arithmetic circuit design. In: Proceedings of design automation test European conference exhibition, pp 1250–1255
Kahng AB, Kang S (2012) Accuracy-configurable adder for approximate arithmetic designs. In: Proceedings of 49th annual design automation conference, pp 820–825
Ye R, Wang T, Yuan F et al (2013) On reconfiguration-oriented approximate adder design and its application. In: Proceedings of international conference on computer-aided design, pp 48–54
Shafique M, Ahmad W, Hafiz R et al (2015) A low latency generic accuracy configurable adder. In: Proceedings of 52nd annual design automation conference, p 86
Hanif MA, Hafiz R, Hasan O, et al (2017) QuAd: design and analysis of quality-area optimal low-latency approximate Adders. In: 2017 54th ACM/EDAC/IEEE design automation conference (DAC) pp 1–6
Liang J, Han J, Lombardi F (2013) New metrics for the reliability of approximate and probabilistic adders. IEEE Trans Comput 62(9):1760–1771
Gonzalez RC, Woods RE (2008) Digital image processing, 3rd, edn. Pearson Education, Upper Saddle River
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Hanif, M.A., Hafiz, R., Shafique, M. (2019). Configurable Models and Design Space Exploration for Low-Latency Approximate Adders. In: Reda, S., Shafique, M. (eds) Approximate Circuits. Springer, Cham. https://doi.org/10.1007/978-3-319-99322-5_1
Download citation
DOI: https://doi.org/10.1007/978-3-319-99322-5_1
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-99321-8
Online ISBN: 978-3-319-99322-5
eBook Packages: EngineeringEngineering (R0)