Synthesis Techniques for Approximation Circuits

Abstract

This chapter explains an important step in the approximate computing IC design flow—approximation-aware automated synthesis methodologies. Broadly speaking, automated synthesis is the process of converting a behavioral description of a design into a structural netlist targeted to a production technology. The technology independent behavioral description is typically specified in a high level language such as Verilog or VHDL using higher level language semantics such as Register Transfer Level specification. The synthesis tool parses this input, with optional design constraints such as limits in timing/area/power, and builds an internal Boolean network. Further, several optimization techniques are used to minimize the cost metrics associated with the targeted technology and finally the netlist is written out. The underlying synthesis process remains the same in the context of approximate computing too. However, approximate computing can also improve the efficiency of a circuit in terms of speed and area by relaxing the constraints on computational accuracy. Hence, an approximation synthesis tool is able to provide much better optimization compared to a conventional synthesis tool since the functional equivalence need not be maintained. An outline of the approximation synthesis design flow is shown in Fig. 5.1. It has to be noted that a conventional equivalence checking tool typically employed in the post-synthesis stage will not be useful with an approximated netlist. Rather, one must use special approximation-aware equivalence checking techniques introduced in the previous chapter to prove the equivalence. An automated synthesis technique should read in the behavioral description of the circuit, i.e., the RTL and the error metric specification to come up with the final structural netlist.