Temporal Locality with a Long Interval: Hybrid Memory System for High-Performance and Low-Power

  • Bo-Sung Jung
  • Jung-Hoon LeeEmail author
Part of the Studies in Computational Intelligence book series (SCI, volume 789)


In this paper, the main idea is to design DRAM and PCM hybrid memory system with low power consumption and high performance based on effective temporal locality. PCM has two major drawbacks by write operation. First, the number of write operations is limited. Second, PCM has a longer write operation time than DRAM. On the other hand, DRAM can effectively overcome the disadvantages of PCM. Therefore, a page replacement algorithm suitable for the characteristics of DRAM and PCM is necessary for effective DRAM and PCM hybrid memory operation. For page management considering the characteristics of PCM, we proposed a page management method based on the temporal locality of a write reference center. In this paper, pages with the temporal locality that are referenced at short intervals will be managed with hybrid memory; pages with temporal locality that are referenced at long intervals are managed by the proposed buffer system. Furthermore, a hot page is defined by a write operation and a buffer system, and this page is managed in DRAM to reduce the overhead of PCM. According to the simulation results, the proposed hybrid memory achieved performance improvement from about 13 and 10% from Energy-delay product compared with CLOCK-DWF and CLOCK-HM.


Hybrid memory Memory architecture Temporal locality Low-power Performance 



This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the ministry of Education, Science and Technology (NRF-2014R1A1A4A01008504).


  1. 1.
    Ma, K., Li, X., et al.: Incidental computing on IoT nonvolatiel processors. In: Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-50 ‘17, pp. 204–218 (2017)Google Scholar
  2. 2.
    Sparsh, M., Jeffrey, S.V.: A survey of software techniques for using non-volatile memories for storage and main memory systems. IEEE Trans. Parallel Distrib. Syst. 27(5), 1537–1550 (2016)CrossRefGoogle Scholar
  3. 3.
    Prabhu, M., Rajarajan S., Suresh, K.S.: Proposed hybrid memory using DRAM and PCM to attain better performance. Am. Eurasian J. Sci. Res., 99–103 (2013)Google Scholar
  4. 4.
    Jang, S.I., Yoon, S.K., et al.: Data classification management with its interfacing structure for hybrid SLC/MLC PRAM main memory. Comput. J. 58(11), 2852–2863 (2015)CrossRefGoogle Scholar
  5. 5.
    Qureshi, M.K., Vijayalakshmi, S., Rivers, J.A.: Scalable high performance main memory system using phase-change memory technology. In: Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 24–33 (2009)Google Scholar
  6. 6.
    Palangappa, P.M., Li, J., Mohanram, K.: WOM-Code solutions for low latency and high endurance in phase change memory. IEEE Trans. Comput. 65(4), 1025–1040 (2016)MathSciNetCrossRefGoogle Scholar
  7. 7.
    Awad, A., Kettreing B., Solihin, Y.: Non-volatile memory host controller interface performance analysis in high-performance I/O systems. In: 2015 IEEE International Symposium on ISPASS, pp. 145–153 (2015)Google Scholar
  8. 8.
    Yoon, S.K., Jung K.S., et al.: Hot-cold data filtering and management for PRAM based memory-storage unified system. In: 2017 IEEE International Conference on Systems, Man, and Cybernetics (SMC), pp. 1609–1614 (2017)Google Scholar
  9. 9.
    Khouzani, H.A., Yang, C., Hu, J.: Improving performance and lifetime of DRAM-PCM hybrid main memory through a proactive page allocation strategy. In: 2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 508–513 (2015)Google Scholar
  10. 10.
    Lee, S.Y., Bahn, H.K., Noh, S.H.: CLOCK-DWF: a write-history-aware page replacement algorithm for hybrid PCM and DRAM memory architectures. IEEE Trans. Comput. 63(9), 2187–2200 (2014)MathSciNetCrossRefGoogle Scholar
  11. 11.
    Khouzani, H.A., Hosseini, F.S., Yang, C.: Segment and conflict aware page allocation and migration in DRAM-PCM hybrid main memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9), 1458–1470 (2016)CrossRefGoogle Scholar
  12. 12.
    Park, K.Y., Yoon, S.K., Kim, S.D.: Selective data buffering module for unified hybrid storage system. In: 14th International Conference on Computer and Information Science, pp. 173–178 (2015)Google Scholar
  13. 13.
    Chen, C., An, J.: DRAM write-only-cache for improving lifetime of phase change memory. In: International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1–4 (2016)Google Scholar
  14. 14.
    Lee, M.H., Kang, D.H., et al.: M-CLOCK: migration-optimized page replacement algorithm for hybrid DRAM and PCM memory architecture. In: Proceedings of the 30th Annual ACM Symposium on Applied Computing, pp. 2001–2006 (2015)Google Scholar
  15. 15.
    Cai, X., Ju, L., et al.: A novel page caching policy for PCM and DRAM of hybrid memory architecture. In: 13th International Conference on Embedded Software and Systems (ICESS), pp. 67–73 (2016)Google Scholar
  16. 16.
    Seok, H.C., Park, Y.W., Park, K.H.: Migration based page caching algorithm for a hybrid main memory of DRAM and PRAM. In: Proceedings of the 2011 ACM Symposium on Applied Computing, SAC ‘11, pp. 595–599 (2011)Google Scholar
  17. 17.
    Corbato, F.J.: A paging experiment with the multics system, in Honor of P.M. Morse, pp. 217–228. MIT Press, Cambridge (1968)Google Scholar
  18. 18.
  19. 19.
    Jiang, L., Zhang, Y., Yang, J.: Mitigating write disturbance in super-dense phase change memories. Proceedings of the 2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN ‘14, pp. 216–227 (2014)Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of Control and InstrumentationGyeongsang National UniversityJinjuKorea
  2. 2.ERI, Department of Control and InstrumentationGyeongsang National UniversityJinjuKorea

Personalised recommendations