Abstract
Simulation is the most widely used form of validation using billions of random and pseudo-random tests in the traditional design flow. A critical problem in post-silicon debug is to generate efficient tests that both activate requisite coverage goal on the target hardware as well as produce results that are observable through a given on-chip design-for-debug architecture. Unfortunately, such tests cannot be generated directly from register-transfer level (RTL) models, both due to design complexity and due to bugs in the design itself. In this chapter, we discuss a directed test generation approach which facilities the observation of expected outputs of the generated tests using the traced signals. The proposed approach uses transaction-level models (TLM) for post-silicon test generation. The basic idea is to transform an RTL assertion as well as observability constraints to create a TLM assertion with observability constraints. The TLM assertion/property would be used to enable TLM analysis to generate post-silicon tests. Finally, the TLM test would be translated to an RTL test that is debug-friendly. In this chapter, we provide case studies from a number of different design classes to demonstrate the flexibility and effectiveness of the approach.
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Notes
- 1.
For some assertions like \(P_{i} \rightarrow \) \(P_{j}\), backward traversal from \(P_{i}\) and forward traversal from \(P_{j}\) would be beneficial. However, in most of the cases performing one of them is enough.
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Farahmandi, F., Mishra, P. (2019). Observability-Aware Post-Silicon Test Generation. In: Mishra, P., Farahmandi, F. (eds) Post-Silicon Validation and Debug. Springer, Cham. https://doi.org/10.1007/978-3-319-98116-1_7
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