Abstract
Effective post-silicon validation of modern SoC designs requires careful upfront planning. This activity, referred to as post-silicon readiness, is one of the most elaborate and time-consuming components of post-silicon validation. This chapter discusses various facets of readiness activities performed in current industrial practice. We delve specifically into one key readiness activity: instrumentation of the design with additional hardware for effective post-silicon observability.
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Ray, S. (2019). SoC Instrumentations: Pre-Silicon Preparation for Post-Silicon Readiness. In: Mishra, P., Farahmandi, F. (eds) Post-Silicon Validation and Debug. Springer, Cham. https://doi.org/10.1007/978-3-319-98116-1_2
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DOI: https://doi.org/10.1007/978-3-319-98116-1_2
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