Abstract
Design-for-Debug (DFD) hardware aims at increasing the visibility into the internal functioning of the chip, through limited additional hardware resources. The large volume of data generated due to near-native speeds offered by the sample chip overwhelms the meager on-chip resources such as trace buffers and transmission links available for the DFD hardware. This significantly hampers the efficiency of post-silicon debug. In order to overcome this, several intelligent compression techniques have been proposed to reduce the volume of such data without significantly increasing the area overhead of the DFD hardware. The techniques cut across a gamut of post-silicon validation methodologies such as run-stop debug and at-speed debug. These techniques also use a variety of intelligent lossless and lossy schemes, some of which are tailored specifically to post-silicon validation in order to achieve impressive compression ratios.
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Chandran, S., Panda, P.R. (2019). Debug Data Reduction Techniques. In: Mishra, P., Farahmandi, F. (eds) Post-Silicon Validation and Debug. Springer, Cham. https://doi.org/10.1007/978-3-319-98116-1_11
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DOI: https://doi.org/10.1007/978-3-319-98116-1_11
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