Advertisement

Three-Level Neutral Point Clamped ZVS-PWM Converter

  • Ivo BarbiEmail author
  • Fabiana Pöttker
Chapter
Part of the Power Systems book series (POWSYS)

Abstract

This chapter studies the Three Level, Zero Voltage Switching, Pulse-Width-Modulated (TL-ZVS-PWM) dc–dc converter, which main attribute is that the maximum voltage across the switches is half of the input voltage. After the introduction of the power converter topology, qualitative analysis and description of operation, along with topological states for each time interval and relevant waveforms are presented. Then, quantitative analysis, focusing on static gain and soft-commutation are discussed. The necessary equations for the design of the parameters involved in the soft-commutation are obtained. Finally, numerical examples to illustrate the theoretical analysis, numerical simulations and proposed exercises with solutions are presented in the text.

Nomenclature

Vi

Input DC voltage

Vo

Output DC voltage

Po

Output power

Co

Output filter capacitor

Lo

Output filter inductor

Ro

Output load resistor

PWM

Pulse width modulation

ZVS

Zero voltage switching

q

Static gain

D

Duty cycle

Dnom

Nominal duty cycle

Def

Effective duty cycle

∆D

Duty cycle loss

fs

Switching frequency

Ts

Switching period

td

Dead time

T

Transformer

n

Transformer turns ratio

\( {\text{v}}^{\prime}_{\text{o}} \) (\( {\text{V}}^{\prime}_{\text{o}} \))

Output voltage referred to the transformer primary side and its average value

io

Output current

\( {\text{I}}^{\prime}_{\text{o}} \)\( \left( {\overline{{{\text{I}}_{\text{o}}^{{\prime }} }} } \right) \)

Average output current referred to the primary side and its normalized value

\( {\text{I}}^{\prime}_{\text{o}} \)crit

Critical average output current referred to the primary side

S1, S2, S3 and S4

Switches

vg1, vg2, vg3 and vg4

Switches S1, S2, S3 and S4 drive signals, respectively

D1, D2, D3 and D4

Diodes in anti-parallel to the switches (MOSFET—intrinsic diodes)

DC1, DC2

Clamping diodes

C = C1 = C2 = C3 = C4

Capacitors in parallel to the switches (MOSFET—intrinsic capacitors)

Lr

Resonant inductor

Cr

Resonant capacitor

iLr peak

Resonant inductor peak current

vCr peak

Resonant inductor peak voltage

Lc

Commutation inductor (may be the transformer leakage inductance or an additional inductor, if necessary)

iLc

Commutation inductor current

ωo

Resonant frequency

vC1, vC2, vC3 and vC4

Capacitors voltage

vab

Ac voltage, between points “a” and “b”

vS1, vS2, vS3 and vS4

Voltage across the switches

iS1, iS2, iS3 and iS4

Current in the switches

iC1, iC2, iC3 and iC4

Current in the capacitors

∆T

Time interval in which vab = ±Vi

∆t2

Time interval of the first and fourth step of operation in DCM

∆t10

Time interval of the first step of operation in CCM (t1–t0)

∆t21

Time interval of the second step of operation in CCM (t2–t1)

∆t32

Time interval of the third step of operation in CCM (t3–t2)

∆t43

Time interval of the fourth step of operation in CCM (t4–t3)

∆t54

Time interval of the fifth step of operation in CCM (t5–t4)

∆t65

Time interval of the sixth step of operation in CCM (t6–t5)

∆t76

Time interval of the seventh step of operation in CCM (t7–t6)

∆t87

Time interval of the eighth step of operation in CCM (t8–t7)

IS14 RMS\( \left( {\overline{{{\text{I}}_{{{\text{S}}14\,{\text{RMS}}}} }} } \right) \)

Switches S1 and S4 RMS current and its normalized value

IS23 RMS\( \left( {\overline{{{\text{I}}_{{{\text{S}}23\,{\text{RMS}}}} }} } \right) \)

Switches S2 and S3 RMS current and its normalized value

ID1234\( \left( {\overline{{{\text{I}}_{{{\text{D}}1 2 3 4}} }} } \right) \)

Diodes D1, D2, D3 and D4 average current and its normalized value

IDC12\( \left( {\overline{{{\text{I}}_{\text{DC12}} }} } \right) \)

Clamping diodes average current and its normalized value

Reference

  1. 1.
    Pinheiro, J.R., Barbi, I.: The Three-Level ZVS-PWM DC-to-DC converter. IEEE Trans. Power Electron. 8(4), 486–492 (1993)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Federal University of Santa CatarinaFlorianópolisBrazil
  2. 2.Department of ElectronicsFederal University of Technology—ParanáCuritibaBrazil

Personalised recommendations