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Asymmetric Half-Bridge ZVS-PWM Converter

  • Ivo BarbiEmail author
  • Fabiana Pöttker
Chapter
Part of the Power Systems book series (POWSYS)

Abstract

The aim of this chapter is to provide the reader with knowledge about the asymmetric half-bridge zero voltage switching, pulse width modulation, converter (A-HB-ZVS-PWM). After the presentation of the power converter topology, the qualitative analysis is done, which includes the description of operation, topological states for each time interval and relevant waveforms. Subsequently, quantitative analysis focusing on static gain and soft-commutation are presented. The necessary equations for the design of the parameters involved in the soft-commutation are obtained. Solved problems to illustrate the theoretical analysis, proposed exercises with solutions and numerical simulations are also included in the text.

Nomenclature

Vi

Input dc voltage

Vo

Output dc voltage

Po

Output power

Co

Output filter capacitor

Lo

Output filter inductor

Ro

Output load resistor

ZVS

Zero voltage switching

q

Static gain

D

Duty cycle

Dnom

Nominal duty cycle

fs

Switching frequency

Ts

Switching period

td

Dead time

T

Transformer

n

Transformer turns ratio

\( {\text{v}}_{\text{o}}^{\prime } \) (\( {\text{V}}_{\text{o}}^{\prime } \))

Output DC voltage referred to the transformer primary side, and its average value

Ce1, Ce2

DC bus capacitors

Ceq

Equivalent DC bus capacitors (Ceq = Ce1 + Ce2)

vCe1, vCe2 (VCe1, VCe1)

DC bus capacitors voltage and its average value

∆vCeq

Equivalent DC bus capacitors voltage ripple

io

Output current

\( {\text{I}}_{\text{o}}^{\prime } \)

Average output current referred to the primary side of the transformer

\( {\text{I}}_{\text{o}}^{\prime } \)crit

Critical average output current referred to the primary side of the transformer

I1

Magnetizing inductance current at the end of time interval 1

I2

Magnetizing inductance current at the end of time interval 4

S1 and S2

Switches

IS1 and IS2

Switches commutation current, respectively

vg1 and vg2

Switches S1 and S2 gate signals, respectively

D1, D2

Diodes in anti-parallel to the switches (MOSFET—intrinsic diodes)

C1, C2

Capacitors in parallel to the switches (MOSFET—intrinsic capacitors)

C

Capacitance in parallel to the switches C = C1 = C2

Lc

Commutation inductance

iLc

Commutation inductor current

vLc

Commutation inductor voltage

Lm

Transformer magnetizing inductance

iLm

Transformer magnetizing inductance current

ILm

Transformer magnetizing inductance average current

∆iLm

Transformer magnetizing inductance current ripple

vab

AC voltage, between points “a” and “b”

vS1, vS2

Voltage across the switches

iS1, iS2

Current on the switches

iC1, iC2

Current in the capacitors

∆ta

Time interval of the first and second step of operation

∆tb

Time interval of the fourth and fifth step of operation

∆tc

Time interval of the third second step of operation

∆td

Time interval of the sixth step of operation

IS1 RMS\( \left( {\overline{{{\text{I}}_{{{\text{S}}1{\text{ RMS}}}} }} } \right) \)

Switch S1 RMS current and its normalized value

IS2 RMS\( \left( {\overline{{{\text{I}}_{{{\text{S}}2{\text{ RMS}}}} }} } \right) \)

Switch S2 RMS current and its normalized value

Reference

  1. 1.
    Imbertson, P., Mohan, N.: Asymmetrical duty cycle permits zero switching loss in PWM circuits with no conduction loss penalty. In: IEEE, pp. 1061–1066 (1991 October)Google Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Federal University of Santa CatarinaFlorianópolisBrazil
  2. 2.Department of ElectronicsFederal University of Technology—ParanáCuritibaBrazil

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