Soft Commutation Isolated DC-DC Converters pp 271-295 | Cite as

# Asymmetric Half-Bridge ZVS-PWM Converter

## Abstract

The aim of this chapter is to provide the reader with knowledge about the asymmetric half-bridge zero voltage switching, pulse width modulation, converter (A-HB-ZVS-PWM). After the presentation of the power converter topology, the qualitative analysis is done, which includes the description of operation, topological states for each time interval and relevant waveforms. Subsequently, quantitative analysis focusing on static gain and soft-commutation are presented. The necessary equations for the design of the parameters involved in the soft-commutation are obtained. Solved problems to illustrate the theoretical analysis, proposed exercises with solutions and numerical simulations are also included in the text.

## Nomenclature

- V
_{i} Input dc voltage

- V
_{o} Output dc voltage

- P
_{o} Output power

- C
_{o} Output filter capacitor

- L
_{o} Output filter inductor

- R
_{o} Output load resistor

- ZVS
Zero voltage switching

- q
Static gain

- D
Duty cycle

- D
_{nom} Nominal duty cycle

- f
_{s} Switching frequency

- T
_{s} Switching period

- t
_{d} Dead time

- T
Transformer

- n
Transformer turns ratio

- \( {\text{v}}_{\text{o}}^{\prime } \) (\( {\text{V}}_{\text{o}}^{\prime } \))
Output DC voltage referred to the transformer primary side, and its average value

- C
_{e1}, C_{e2} DC bus capacitors

- C
_{eq} Equivalent DC bus capacitors (C

_{eq}= C_{e1}+ C_{e2})- v
_{Ce1}, v_{Ce2}(V_{Ce1}, V_{Ce1}) DC bus capacitors voltage and its average value

- ∆v
_{Ceq} Equivalent DC bus capacitors voltage ripple

- i
_{o} Output current

- \( {\text{I}}_{\text{o}}^{\prime } \)
Average output current referred to the primary side of the transformer

- \( {\text{I}}_{\text{o}}^{\prime } \)
_{crit} Critical average output current referred to the primary side of the transformer

- I
_{1} Magnetizing inductance current at the end of time interval 1

- I
_{2} Magnetizing inductance current at the end of time interval 4

- S
_{1}and S_{2} Switches

- I
_{S1}and I_{S2} Switches commutation current, respectively

- v
_{g1}and v_{g2} Switches S

_{1}and S_{2}gate signals, respectively- D
_{1}, D_{2} Diodes in anti-parallel to the switches (MOSFET—intrinsic diodes)

- C
_{1}, C_{2} Capacitors in parallel to the switches (MOSFET—intrinsic capacitors)

- C
Capacitance in parallel to the switches C = C

_{1}= C_{2}- L
_{c} Commutation inductance

- i
_{Lc} Commutation inductor current

- v
_{Lc} Commutation inductor voltage

- L
_{m} Transformer magnetizing inductance

- i
_{Lm} Transformer magnetizing inductance current

- I
_{Lm} Transformer magnetizing inductance average current

- ∆i
_{Lm} Transformer magnetizing inductance current ripple

- v
_{ab} AC voltage, between points “a” and “b”

- v
_{S1}, v_{S2} Voltage across the switches

- i
_{S1}, i_{S2} Current on the switches

- i
_{C1}, i_{C2} Current in the capacitors

- ∆t
_{a} Time interval of the first and second step of operation

- ∆t
_{b} Time interval of the fourth and fifth step of operation

- ∆t
_{c} Time interval of the third second step of operation

- ∆t
_{d} Time interval of the sixth step of operation

- I
_{S1 RMS}\( \left( {\overline{{{\text{I}}_{{{\text{S}}1{\text{ RMS}}}} }} } \right) \) Switch S

_{1}RMS current and its normalized value- I
_{S2 RMS}\( \left( {\overline{{{\text{I}}_{{{\text{S}}2{\text{ RMS}}}} }} } \right) \) Switch S

_{2}RMS current and its normalized value

## Reference

- 1.Imbertson, P., Mohan, N.: Asymmetrical duty cycle permits zero switching loss in PWM circuits with no conduction loss penalty. In: IEEE, pp. 1061–1066 (1991 October)Google Scholar