Abstract
In this chapter, the topological description and analytical analysis of the operational transconductance amplifiers proposed in this work are presented. The proposed topologies are addressed with proper implementations at sizing level, design strategies, and simulation level results, compounding the respective analytical analyses and small-signal equivalent circuits. The fundamental elements and notions of the basic voltage-combiner structure are described in Sect. 3.1. The voltage-combiner -biased OTA is described in Sect. 3.2. The voltage-combiner-biased OTA improved with current starving is described in Sect. 3.3. The folded voltage-combiner-biased OTA, for lower-supply voltages, is described in Sect. 3.4. The fully dynamic OTA biased by voltage-combiners, specifically designed for analog-to-digital conversion architectures, is described in Sect. 3.5. Finally, the noise modeling is addressed in Sect. 3.6.
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Póvoa, R.F.S., Goes, J.C.d.P., Horta, N.C.G. (2019). Proposed Family of CMOS Amplifiers. In: A New Family of CMOS Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain. Springer, Cham. https://doi.org/10.1007/978-3-319-95207-9_3
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DOI: https://doi.org/10.1007/978-3-319-95207-9_3
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