Abstract
Geometric camera calibration plays a key role in machine vision to detect and measure objects. This work presents the high level synthesis (HLS) design of a camera calibration algorithm on an FPGA. By optimizing the C description, we were able to improve execution performance of the naive implementation by about 1.3–1.5 times. Especially, it was shown that the way of describing multi-dimensional arrays has a large impact on synthesis results. However, the implementation requires more hardware resources than available on the chip. A large amount of arithmetic operations become a bottleneck for FPGA resources due to the calculation of all parameters.
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Uetsuhara, K., Nagayama, H., Shibata, Y., Oguri, K. (2019). Discussion on High Level Synthesis FPGA Design of Camera Calibration. In: Barolli, L., Javaid, N., Ikeda, M., Takizawa, M. (eds) Complex, Intelligent, and Software Intensive Systems. CISIS 2018. Advances in Intelligent Systems and Computing, vol 772. Springer, Cham. https://doi.org/10.1007/978-3-319-93659-8_48
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DOI: https://doi.org/10.1007/978-3-319-93659-8_48
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