Skip to main content

Overview About Radiation–Matter Interaction Mechanisms and Mitigation Techniques

  • Conference paper
  • First Online:
Proceedings of the 3rd Brazilian Technology Symposium (BTSym 2017)

Abstract

This work presents a general overview about the origin and manifestation of ionizing radiation-induced effects over CMOS technology-based semiconductor structures. From the characterization of radiation–matter interaction mechanisms and effects, this work summarizes the set of design strategies described in the literature for radiation hardened electronic implementation, considering system level, block level, and device level approaches. Additionally, a final case study is presented characterizing the Total Ionizing Dose TID tolerant operation of the Diamond MOSFET transistor as an innovative alternative of non-standard MOSFET’s layout for space applications.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Stassinopoulos, E.G., Raymond, J.P.: The space radiation environment for electronics. Proc. IEEE, pp. 1423–1442 (1988)

    Google Scholar 

  2. Johnston, A.H., Radiation effects in advanced microelectronics technologies. IEEE Trans. Nucl. Sci. (1998)

    Google Scholar 

  3. Johnston, A.H.: Scaling and technology issues for soft error rates. In: 4th Annual Research Conference on Reliability (2000)

    Google Scholar 

  4. Koons, H.C., et al.: The impact of the space environment on space systems. In: 6th Spacecrat Charging Technology Conference (2000)

    Google Scholar 

  5. Hughes, H.L., Benedetto, J.M.: Radiation effects and hardening of MOS technology: devices and circuits. IEEE Trans. Nucl. Sci. (2003)

    Google Scholar 

  6. Camplani, A., Shojaii, S., Shrimali, H., Stabile, A., Liberali, V.: CMOS IC radiation hardening by design. Facta Univ.—Ser.: Electron. Energ., pp. 251–258 (2014)

    Google Scholar 

  7. Bezhenova, V., Michalowska-Forsyth, A.M.: Effects of ionizing radiation on integrated circuits. Elektrotech. Informationstechnik, pp. 39–42 (2016)

    Google Scholar 

  8. Maurer, R.H., Fraeman, M.E., Martin, M.N., Roth, D.R.: Harsh environments: space radiation environment, effects, and mitigation. In: Johns Hopkins APL Technical Digest (2008)

    Google Scholar 

  9. Karnick, T., Hazucha, P., Patel, J.: Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Trans. Dependable Secure Comput. (2004)

    Google Scholar 

  10. Munteanu, D., Autran, J.-L.: Modeling and simulation of single-event effects in digital devices and ICs. IEEE Trans. Nucl. Sci. (2008)

    Google Scholar 

  11. Adell, P., et al.: Analysis of single-event transients in analog circuits. IEEE Trans. Nucl. Sci. (2000)

    Google Scholar 

  12. Messenger, G.: Collection of charges on junction nodes from ion tracks. IEEE Trans. Nucl. Sci. (1982)

    Google Scholar 

  13. Srour, J.S., Marshall, C., Marshall, P.W.: Review of displacement damage effects on silicon devices. IEEE Trans. Nucl. Sci. (2003)

    Google Scholar 

  14. Dubrova, E.: Fault Tolerant Design: An Introduction. Sweden Kluwer Academic Publishers (2008)

    Google Scholar 

  15. Nicolaidis, M.: Design of soft error mitigation. IEEE Trans. Device Mater. Reliab. (2005)

    Google Scholar 

  16. Todd, B., Uznanski, S.: Radiation risks and mitigation in electronic systems. In: CAS-CERN Accelerator School: Power Converters (2015)

    Google Scholar 

  17. Gurudatt Kulkarni, M.G., Wani, M.L.: Review on redundancy in electronics. Int. J. Eng. Comput. Sci. (2013)

    Google Scholar 

  18. Pan, D., Li, H.W., Wilamowski, B.M.: A radiation-hard phase-locked loop. In: International Symposium on Industrial Electronics ISIE (2003)

    Google Scholar 

  19. Lyons, R.E., Vanderkulk, W.: The use of triple modular redundancy to improve computer reliability. IBM J. (1962)

    Google Scholar 

  20. Abraham, J.A., Siewiorek, D.P.: An algorithm for the accurate reliability evaluation of triple modular redundant networks. IEEE Trans. Comput. (1974)

    Google Scholar 

  21. Teifel, J.: Self-voting dual modular redundancy circuits for single-event-transient mitigation. IEEE Trans. Nucl. Sci. (2008)

    Google Scholar 

  22. Engelman, C., Ong, H., Scott, S.L.: The case of modular redundancy in large-scale high performance computing systems. In: 27th IASTED International Conference on Parallel and Distributed Computing and Networks (2009)

    Google Scholar 

  23. Wakerly, J.F.: Microcomputer reliability improvement using triple-modular redundancy. Proc. IEEE (1976)

    Google Scholar 

  24. Mine, H., Hitayama, K.: Reliability analysis and optimal redundancy for majority-voted logic circuits. IEEE Trans. Reliab. (1981)

    Google Scholar 

  25. Hamamatsu, M., Tsuchyia, T., Kikuno, T.: On the reliability of cascaded TMR systems. In: Pacific Rim International Symposium on Dependable Computing (2010)

    Google Scholar 

  26. Rahman, M.H., Rafique, S., Alam, M.S.: A fault tolerant voter circuit for triple modular redundant system. J. Electr. Electron. Eng. (2017)

    Google Scholar 

  27. Adeosun, O.O., Ismaila, W.O., Omotoso, I.O., Adeosun, T.H.: Hybrid modular redundancy network for critical systems. Int. J. Emerg. Technol. Adv. Eng. IJETAE (2012

    Google Scholar 

  28. Alagoz, B.B.: Hierarchical triple-modular redundancy (H-TMR) network for digital systems. In: OncuBilim Algorithm And Systems Labs (2008)

    Google Scholar 

  29. Han, J.: A Fault-Tolerant Technique using quadded logic and quadded transistors. IEEE Trans. VLSI Syst. (2014)

    Google Scholar 

  30. Grace Vimala, E., Nagavalli, V.: Design of quadded logic and quadded transistor using low power consumption. Int. J. Adv. Res. Electr. Electron. Instrum. Eng. (2016)

    Google Scholar 

  31. Han, J., Jonker, P.: A study on fault-tolerant circuits using redundancy. In: Multiconference (2003)

    Google Scholar 

  32. Freeman, H.A., Metze, G.: Fault-tolerant computers using “Dotted Logic—Redundancy Techniques”. IEEE Trans. Comput. (1972)

    Google Scholar 

  33. Beiu, V., Ibrahim, W., Beg, A., Tache, M.: On sizing transistors for threshold voltage variations (2012)

    Google Scholar 

  34. Stabile, A., Liberali, V., Calligaro, C.: Design of a rad-hard library of digital cells for space applications. In: 15th International Conference on Electronics, Circuits and Systems ICECS (2008)

    Google Scholar 

  35. Snoeys, W.J., Gutierrez, T.A.P., Anelli, G.: A new NMOS layout structure for radiation tolerance. IEEE Trans. Nucl. Sci. (2002)

    Google Scholar 

  36. Nowlin, R.N., McEndree, S.R., Wilson, A.L., Alexander, D.R.: A new total-dose-induced parasitic effect in enclosed-geometry transistors. IEEE Trans. Nucl. Sci. (2005)

    Google Scholar 

  37. Gimenez, S.P., Galembeck, E.H.S., Renaux, C., Flandre, D.: Impact of using the octogonal layout for SOI MOSFETs in a high temperature environment. IEEE Trans. Dev. Mater. Reliab. (2015)

    Google Scholar 

  38. Seixas, L.E., Gonzalez, O.L., Souza, R.R.N., Finco, S., Vaz, R.G., da Silva, G.A., Gimenez, S.P.: Improving MOSFETs tolerance through diamond layout style. IEEE Trans. Dev. Mater. Reliab. (2017)

    Google Scholar 

  39. Seixas, L.E., Finco, S., Silveira, M.A.G, Medina, N.H., Gimenez, S.P.: Study of proton radiation effects among diamond and rectangular gate MOSFETs layouts. Mater. Res. Exp. (2017)

    Google Scholar 

  40. Gimenez, S.P., Correia, M.M., Neto, E.D., Silva, C.R.: An innovative ellipsoidal layout style to further boost the electrical performance to MOSFETs. IEEE Electr. Dev. Lett. (2015)

    Google Scholar 

  41. Gimenez, S.P.: Layout Techniques for MOSFETs (Synthesis Lectures on Emerging Engineering Technologies). Morgan & Claypoole Books (2016)

    Google Scholar 

  42. Gimenez, S.P.: Diamond MOSFET: an innovative layout to improve performance of ICs. Solid-State Electr. (2010)

    Google Scholar 

  43. Gimenez, S.P., Alati, D.M.: Electrical behavior of the diamond layout style for MOSFETs in X-rays ionizing radiation environments. Microelectron. Eng. (2015)

    Google Scholar 

  44. Gimenez, S.P., et al.: Diamond layout style impact on SOI MOSFET in high temperature environment. Microelectron. Reliab. (2015)

    Google Scholar 

  45. Gimenez, S.P., Flandre, D. et al.: Using diamond layout style to boost MOSFET frequency response of analogue IC. Electron. Lett. (2014)

    Google Scholar 

  46. Gimenez, S.P. et al.: Compact diamond MOSFET model accounting for PAMDLE applicable down 150 nm node. Electron. Lett. (2014)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to R. N. S. Raphael .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer International Publishing AG, part of Springer Nature

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Raphael, R.N.S. et al. (2019). Overview About Radiation–Matter Interaction Mechanisms and Mitigation Techniques. In: Iano, Y., Arthur, R., Saotome, O., Vieira Estrela, V., Loschi, H. (eds) Proceedings of the 3rd Brazilian Technology Symposium. BTSym 2017. Springer, Cham. https://doi.org/10.1007/978-3-319-93112-8_23

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-93112-8_23

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-93111-1

  • Online ISBN: 978-3-319-93112-8

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics