Skip to main content

Hardware Security and Trust: Logic Locking as a Design-for-Trust Solution

  • Chapter
  • First Online:
The IoT Physical Layer

Abstract

Ever-increasing design complexity and the skyrocketing cost of setting up a foundry have led to the globalization of the integrated circuit (IC) supply chain. A globalized and distributed IC supply fosters security threats such as reverse engineering, piracy, and hardware Trojans, and forces the stakeholders to revisit the trust at various steps in the IC design and fabrication flow. Among the ensemble of solutions proposed to address hardware-related trust issues, logic locking has gained significant interest from the research community. A series of defense techniques and attacks have been developed over the past few years. This chapter presents a comprehensive survey of recent research efforts in the field of logic locking. The emphasis is on the subtle difference between the logic locking attacks/countermeasures in terms of the threat models employed and strengths/vulnerabilities of existing logic locking techniques.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 139.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    Researchers have also used the terms “logic obfuscation” [23] and “logic encryption” [22, 26] for this purpose.

References

  1. A. Baumgarten, A. Tyagi, J. Zambreno, Preventing IC piracy using reconfigurable logic barriers. IEEE Des. Test Comput. 27(1), 66–75 (2010)

    Article  Google Scholar 

  2. M. Berry, G. John, Outsourcing Test—What are the most valuable engagement periods? (2014), http://www.amkor.com/go/outsourcing-test. Accessed 16 May 2016

  3. S. Bhunia, M.S. Hsiao, M. Banga, S. Narasimhan, Hardware trojan attacks: threat analysis and countermeasures. Proc. IEEE 102(8), 1229–1247 (2014)

    Article  Google Scholar 

  4. D.S. Board, Defense Science Board (DSB) study on High Performance Microchip Supply (2005), www.acq.osd.mil/dsb/reports/ADA435563.pdf. Accessed 16 March 2015

  5. M.L. Bushnell, V.D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits (Kluwer Academic Publishers, Boston, 2000). ISBN 9780792379911

    Google Scholar 

  6. A.E. Caldwell, H.J. Choi, A.B. Kahng, S. Mantik, M. Potkonjak, G. Qu, J.L. Wong, Effective iterative techniques for fingerprinting design IP, in Proceedings of the IEEE/ACM Design Automation Conference, 1999, pp. 843–848

    Google Scholar 

  7. R.S. Chakraborty, S. Bhunia, HARPOON: an obfuscation-based SoC design methodology for hardware protection. IEEE Trans. Comput-Aided Design Integr. Circuits Syst. 28(10), 1493–1502 (2009)

    Article  Google Scholar 

  8. R.S. Chakraborty, S. Bhunia, Security against Hardware Trojan through a novel application of design obfuscation, in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2009, pp. 113–116

    Google Scholar 

  9. Chipworks, Reverse engineering software (2016), http://www.chipworks.com/en/technical-competitive-analysis/resources/reerse-engineering-software

  10. B. Colombier, L. Bossuet, Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Comput. Digit. Techniq. 8(6), 274–287 (2014)

    Article  Google Scholar 

  11. S. Dupuis, P. Ba, G.D. Natale, M. Flottes, B. Rouzeyre, A novel hardware logic encryption technique for thwarting illegal overproduction and hardware Trojans, in Proceedings of the IEEE International On-Line Testing Symposium, 2014, pp. 49–54

    Google Scholar 

  12. K.M. Goertzel, B. Hamilton, Integrated circuit security threats and hardware assurance countermeasures. CrossTalk (2013), p. 33

    Google Scholar 

  13. O. Goldreich, Foundations of Cryptography. Basic Tools, vol. 1 (Cambridge University Press, 2001). ISBN 978-0521035361

    Google Scholar 

  14. U. Guin, K. Huang, D. DiMase, J.M. Carulli, M. Tehranipoor, Y. Makris, Counterfeit integrated circuits: a rising threat in the global semiconductor supply chain. Proc. IEEE 102(8), 1207–1228 (2014)

    Article  Google Scholar 

  15. R.W. Jarvis, M.G. McIntyre, Split Manufacturing Method for Advanced Semiconductor Circuits. US Patent 7,195,931 (2007)

    Google Scholar 

  16. A.B. Kahng, J. Lach, W.H. Mangione-Smith, S. Mantik, I.L. Markov, M. Potkonjak, P. Tucker, H. Wang, G. Wolfe, Watermarking techniques for intellectual property protection, in Proceedings of the IEEE/ACM Design Automation Conference, 1998, pp 776–781

    Google Scholar 

  17. R. Karri, J. Rajendran, K. Rosenfeld, M. Tehranipoor, Trustworthy hardware: identifying and classifying hardware Trojans. Computer 43(10), 39–46 (2010)

    Article  Google Scholar 

  18. P. Kocher, J. Jaffe, B. Jun, Differential power analysis, in Advances in Cryptology (Springer, 1999), pp. 388–397

    Google Scholar 

  19. F. Koushanfar, Integrated circuits metering for piracy protection and digital rights management: an overview, in Proceedings of the Great Lakes Symposium on VLSI, 2011, pp. 449–454

    Google Scholar 

  20. Y.W. Lee, N. Touba, Improving logic obfuscation via logic cone analysis, in Proceedings of the Latin-American Test Symposium, 2015, pp. 1–6

    Google Scholar 

  21. S.M. Plaza, I.L. Markov, Solving the third-shift problem in IC piracy with test-aware logic locking. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 34(6), 961–971 (2015)

    Article  Google Scholar 

  22. J. Rajendran, Y. Pino, O. Sinanoglu, R. Karri, Logic encryption: a fault analysis perspective, Proceedings Design, Automation and Test in Europe, 2012, pp. 953–958

    Google Scholar 

  23. J. Rajendran, Y. Pino, O. Sinanoglu, R. Karri, Security analysis of logic obfuscation, in Proceedings of the IEEE/ACM Design Automation Conference, 2012, pp. 83–89

    Google Scholar 

  24. J. Rajendran, M. Sam, O. Sinanoglu, R. Karri, Security Analysis of integrated circuit camouflaging, in Proceedings of the ACM/SIGSAC Conference on Computer & Communications Security, 2013, pp. 709–720

    Google Scholar 

  25. J. Rajendran, O. Sinanoglu, R. Karri, Regaining trust in VLSI design: design-for-trust techniques. Proc. IEEE 102(8), 1266–1282 (2014)

    Article  Google Scholar 

  26. J. Rajendran, H. Zhang, C. Zhang, G. Rose, Y. Pino, O. Sinanoglu, R. Karri, Fault analysis-based logic encryption. IEEE Trans. Comput. 64(2), 410–424 (2015)

    Article  MathSciNet  Google Scholar 

  27. A.P. Room, Silicon Laboratories and ASE announce milestone shipment of 10 million tested integrated circuits (2014), http://www.aseglobal.com/en/News/PressRoomDetail.aspx?ID=45. Accessed 16 May 2016

  28. M. Rostami, F. Koushanfar, R. Karri, A primer on hardware security: models, methods, and metrics. Proc. IEEE 102(8), 1283–1295 (2014)

    Article  Google Scholar 

  29. J. Roy, F. Koushanfar, I.L. Markov, EPIC: ending piracy of integrated circuits, in Proceedings Design, Automation and Test in Europe, 2008, pp. 1069–1074

    Google Scholar 

  30. J.A. Roy, F. Koushanfar, I.L. Markov, Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010)

    Article  Google Scholar 

  31. SEMI, Innovation is at Risk Losses of up to $4 Billion Annually due to IP Infringement (2008), www.semi.org/en/Issues/IntellectualProperty/ssLINK/P043785. Accessed 10 June 2015

  32. K. Shamsi, M. Li, T. Meade, Z. Zhao, D.Z. Pan, Y. Jin, Cyclic obfuscation for creating sat-unresolvable circuits, in Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017, ACM, pp. 173–178

    Google Scholar 

  33. K. Shamsi, M. Li, T. Meade, Z. Zhao, D.Z. Pan, Y. Jin, AppSAT: approximately deobfuscating integrated circuits, in IEEE International Symposium on Hardware Oriented Security and Trust, 2017, pp. 95–100

    Google Scholar 

  34. Y. Shen, H. Zhou, Double dip: Re-evaluating security of logic encryption algorithms. Cryptology ePrint Archive, Report 2017/290, (2017), http://eprint.iacr.org/2017/290

  35. P. Subramanyan, S. Ray, S. Malik, Evaluating the security of logic encryption algorithms, in Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, pp. 137–143

    Google Scholar 

  36. R. Torrance, D. James, The State-of-the-Art in semiconductor reverse engineering, in Proceedings of the IEEE/ACM Design Automation Conference, 2011, pp. 333–338

    Google Scholar 

  37. Y. Xie, A. Srivastava, Mitigating SAT attack on logic locking. IACR Cryptology ePrint Archive 2016, 590 (2016)

    Google Scholar 

  38. X. Xu, B. Shakya, M. Tehranipoor, D. Forte, Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks. Cryptology ePrint Archive, Report 2017/621, 2017, http://eprint.iacr.org/2017/621

  39. M. Yasin, O. Sinanoglu, Evolution of logic locking, in 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2017, pp. 1–6

    Google Scholar 

  40. M. Yasin, B. Mazumdar, S.S. Ali, O. Sinanoglu, Security analysis of logic encryption against the most effective side-channel attack: DPA, in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015, pp. 97–102

    Google Scholar 

  41. M. Yasin, B. Mazumdar, J. Rajendran, O. Sinanoglu, SARLock: SAT attack resistant logic locking, in IEEE International Symposium on Hardware Oriented Security and Trust, 2016, pp. 236–241

    Google Scholar 

  42. M. Yasin, B. Mazumdar, O. Sinanoglu, J. Rajendran, Security analysis of anti-SAT. Cryptology ePrint Archive, Report 2016/896, (2016), http://eprint.iacr.org/2016/896

  43. M. Yasin, J. Rajendran, O. Sinanoglu, R. Karri, On Improving the security of logic locking. IEEE Trans. CAD of Integr. Circuits Syst. (2016)

    Google Scholar 

  44. M. Yasin, S.M. Saeed, J. Rajendran, O. Sinanoglu, Activation of logic encrypted chips: pre-test or post-test?, in Proceedings Design, Automation Test in Europe, 2016, pp. 139–144

    Google Scholar 

  45. M. Yasin, B. Mazumdar, O. Sinanoglu, J. Rajendran, Removal attacks on logic locking and camouflaging techniques. IEEE Trans. Emerg. Topics Comput. 99(0) (2017)

    Google Scholar 

  46. M. Yasin, A. Sengupta, M.T. Nabeel, M. Ashraf, J.J. Rajendran, O. Sinanoglu, Provably-secure logic locking: from theory to practice, in Proceedings of the ACM SIGSAC Conference on Computer and Communications Security, 2017, pp. 1601–1618

    Google Scholar 

  47. M. Yasin, A. Sengupta, B.C. Schafer, Y. Makris, O. Sinanoglu, J.J. Rajendran, What to lock?: functional and parametric locking, in Great Lakes Symposium on VLSI, 2017, pp. 351–356

    Google Scholar 

Download references

Acknowledgements

This work has been supported by the Semiconductor Research Corporation (SRC) under the Abu Dhabi SRC Center of Excellence on Energy-Efficient Electronic Systems (\(ACE^{4}S\)), Contract 2013 HJ2440, with funding from the Mubadala Development Company, Abu Dhabi, UAE.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Muhammad Yasin .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer International Publishing AG, part of Springer Nature

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Yasin, M., Mazumdar, B., Rajendran, J., Sinanoglu, O. (2019). Hardware Security and Trust: Logic Locking as a Design-for-Trust Solution. In: Elfadel, I., Ismail, M. (eds) The IoT Physical Layer. Springer, Cham. https://doi.org/10.1007/978-3-319-93100-5_20

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-93100-5_20

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-93099-2

  • Online ISBN: 978-3-319-93100-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics