Abstract
For modern main memory database systems, the memory bus is the main bottleneck. Specialized hardware components of large NUMA systems, such as HPE’s GRU, make it possible to offload memory transfers. In some cases, this improves the throughput by 30%, but other scenarios suffer from reduced performance. We show which factors influence this tradeoff. Based on our experiments, we present an adaptive prediction model that supports the DBMS in deciding whether to utilize these components. In addition, we evaluate non-coherent memory access as an additional access method and discuss its benefits and shortcomings.
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Notes
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All benchmarks were executed on an SGI UV 300H with 6 TB RAM and eight Intel E7-8890 v2 processors. Our code was compiled with gcc 7.2 at
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Acknowledgments
We thank Martin Boissier and Rainer Schlosser for their helpful input on the estimation model.
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Dreseler, M., Gasda, T., Kossmann, J., Uflacker, M., Plattner, H. (2018). Adaptive Access Path Selection for Hardware-Accelerated DRAM Loads. In: Wang, J., Cong, G., Chen, J., Qi, J. (eds) Databases Theory and Applications. ADC 2018. Lecture Notes in Computer Science(), vol 10837. Springer, Cham. https://doi.org/10.1007/978-3-319-92013-9_1
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DOI: https://doi.org/10.1007/978-3-319-92013-9_1
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