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Adaptive Access Path Selection for Hardware-Accelerated DRAM Loads

  • Markus Dreseler
  • Timo Gasda
  • Jan Kossmann
  • Matthias Uflacker
  • Hasso Plattner
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10837)

Abstract

For modern main memory database systems, the memory bus is the main bottleneck. Specialized hardware components of large NUMA systems, such as HPE’s GRU, make it possible to offload memory transfers. In some cases, this improves the throughput by 30%, but other scenarios suffer from reduced performance. We show which factors influence this tradeoff. Based on our experiments, we present an adaptive prediction model that supports the DBMS in deciding whether to utilize these components. In addition, we evaluate non-coherent memory access as an additional access method and discuss its benefits and shortcomings.

Notes

Acknowledgments

We thank Martin Boissier and Rainer Schlosser for their helpful input on the estimation model.

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Markus Dreseler
    • 1
  • Timo Gasda
    • 1
  • Jan Kossmann
    • 1
  • Matthias Uflacker
    • 1
  • Hasso Plattner
    • 1
  1. 1.Hasso Plattner InstitutePotsdamGermany

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