The FinFET: A Tutorial

Abstract

Ever since Intel launched its successful 22-nm Ivy Bridge CPU chip, establishing nonplanar finFET technology as a viable means of extending Moore’s law, variations of the basic finFET or the nanowire transistor have been introduced into nanoelectronics research and manufacturing efforts at an unprecedented rate.

All members of the finFET family of devices—whether fabricated on a bulk or SOI substrate, or structured as a double- or triple-gate or a nanowire transistor—share the same fundamental operating mechanism: the electric field effect. Drain current is under the control of a gate voltage that modulates the conductivity of the underlying fin or nanowire. This tutorial derives qualitative I-V characteristics for such devices, using intuitive assumptions and principles like Ohm’s law and Poisson’s equation.

It then focuses on the geometric characteristics of nonplanar devices, examining the layout of a typical CMOS standard cell comprising both n- and p-type finFETs. The use of a local interconnect layer to connect adjacent fins is detailed. A section is devoted to explaining why nonplanar devices exhibit higher immunity to short-channel effects (SCEs). To quantify this explanation, the natural screening length parameter λ is introduced and then computed for several common device types.

The tutorial cites a dozen intuitive rules of thumb that engineers and scientists may find useful in evaluating finFET design issues and device trade-offs. During the discussion, key electrical and physical finFET properties are related to their corresponding BSIM-CMG SPICE parameters, including GEOMOD and NFIN.

Glossary

Analog/RF CMOS

As used in this tutorial, it refers to analog circuits (from low- to radio-frequency and even millimeter wave) on a mostly digital CMOS chip. This presents a challenge for the analog designer, since any CMOS fabrication process is optimized for noisy digital logic, not sensitive analog functions such as low-noise amplifiers or wireless transceivers. Digital processes offer simple speed vs. power trade-offs, while analog circuits may need optimizing for gain, linearity, or noise.

BSIM SPICE models

The acronym stands for Berkeley short-channel IGFET (insulated gate) model. Older versions, like BSIM3 and BSIM4, model traditional MOSFETs, up to the 22-nm node. Newer versions like BSIM-CMG model nonplanar devices like the finFET. These models stem from the principles of device physics (like the GCA equations used in this tutorial), rather than purely empirical formulas.

Carrier concentration

In contrast to metallic conductors such as aluminum or copper, semiconductors have two independent charge carriers: electrons and holes. The behavior of diodes, transistors, and other semiconductor devices often hinges upon the relative concentrations of holes (p) and electrons (n), expressed in carriers per cm³. In pure silicon, they are thermally generated in pairs. In this intrinsic state, n and p remain equal. Their product is np = n_i² ≈ 10¹⁰ cm⁻³ at room temperature.

In a p-type substrate, however, the substitution of acceptor atoms (like boron) into the silicon lattice results in an excess of holes. Then p_p > > n_p, indicating an excess of majority-carrier holes over minority-carrier electrons. The product np = n_i² will remain constant under thermal equilibrium (no applied bias or other perturbations).

CD

An acronym familiar to fab engineers, denoting any critical dimension of a feature on a wafer. CDs can be measured in the fab by a CD-SEM. For example, an Intel engineer might plot subthreshold swing as a function of the measured width of a poly line crossing a fin, in nm. This CD is a routine measure of channel length L.

Drain-induced barrier lowering (DIBL)

When the drain bias of a short-channel device increases from low to saturated values, threshold roll-off is aggravated. (The shaded triangles in Fig. 2.1 indicated how roll-off occurs at low drain bias. DIBL occurs at higher V_DS values.) The drain bias affects the potential distribution, lowering barriers to subthreshold conduction. This SCE is measured in mV per volt.

Inversion

In an n-type MOS transistor at the onset of inversion, the concentration of minority electrons flooding into the channel just equals that of holes deep within the p-type substrate. Thus, n_p(0) = p_p(∞), where coordinate 0 refers to the silicon surface. The relative concentration of minority and majority carriers thus becomes inverted. Above this threshold, n_p(0) rises exponentially with surface potential Φ_s.

Permittivity ε₀

Intuitively, the electrical permittivity ε₀ of free space is equal to the capacitance of a cube-shaped parallel-plate capacitor, filled with a vacuum, of 1 cm thickness and 1 cm² area. A fundamental constant, it equals 8.85 × 10⁻¹⁴ F/cm.

PTM SPICE models

The acronym is for predictive technology model , which evolved from predictive modeling efforts at Berkeley, and is now advanced by the Nanoscale Integration and Modeling Group at the Arizona State University. A goal of this group is predictive modeling, applicable to the next generation of technology—not only finFET devices down to 7 nm but even to future carbon nanotube devices.

Silicon on insulator (SOI)

A promising alternative to bulk finFET technology, in which transistors are fabricated directly on a silicon wafer. In SOI technology, an insulating oxide layer (the buried oxide, or BOX) is implanted below the surface of the entire wafer. FinFET transistors are fabricated into the thin layer of silicon left on top. Due to the BOX, there is little or no parasitic capacitance to the substrate. Another advantage of SOI wafers is that no well is needed around p-type devices. The trade-off is a higher SOI base wafer cost—as much as 4× higher than bulk.

Subthreshold swing (SS)

Subthreshold current is one of the worst SCEs. It makes a short-channel transistor too leaky to turn completely off. Since this current falls off exponentially as V_GS drops below V_T, it is ordinarily plotted on a log scale. The slope of this log-linear plot is then ∂log(I_DS)/∂V_GS. In the lab, it is more convenient to measure the reciprocal of this slope, in mV per decade of current, often called subthreshold swing. It has a theoretical minimum of 60 mV/decade—which Intel nearly met with its 22-nm finFET. Devices which swing higher are more leaky.

Verilog-A

An addition to the Verilog digital hardware description language was able to model analog circuits as well. It includes an analog code block, as well as the usual always. Since BSIM-CMG is written in Verilog-A, it can use classic case syntax, like case(GEOMOD), to check a parameter and set values accordingly. It can also use analog operators like ddt(q) to differentiate charge, yielding current.