Compiling for VLIW DSPs

  • Christoph W. KesslerEmail author


This chapter describes fundamental compiler techniques for VLIW DSP processors. We begin with a review of VLIW DSP architecture concepts, as far as relevant for the compiler writer. As a case study, we consider the TI TMS320C6x™ clustered VLIW DSP processor family. We survey the main tasks of VLIW DSP code generation, discuss instruction selection, cluster assignment, instruction scheduling and register allocation in some greater detail, and present selected techniques for these, both heuristic and optimal ones. Some emphasis is put on phase ordering problems and on phase coupled and integrated code generation techniques.



The author thanks Mattias Eriksson and Dake Liu for discussions and commenting on a draft of this chapter. The author also thanks Eric Stotzer from Texas Instruments for interesting discussions about code generation for the TI ’C6x DSP processor family.

This work was funded by Vetenskapsrådet (project Integrated Software Pipelining), SSF (project DSP platform for emerging telecommunication and multimedia) and by SeRC, Parallel Software and Data Engineering (


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Authors and Affiliations

  1. 1.Department of Computer Science (IDA)Linköping UniversityLinköpingSweden

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