Programmable Architectures for Histogram of Oriented Gradients Processing

  • Colm Kelly
  • Roger WoodsEmail author
  • Moslem Amiri
  • Fahad Siddiqui
  • Karen Rafferty


There is an increasing demand for high performance image processing platforms based on field programmable gate array (FPGA). The Histogram of Orientated Gradients (HOG) algorithm is a feature descriptor algorithm used in object detection for many security applications. The chapter examines the implementation of this key algorithm using an FPGA-based soft-core architecture approach. Firstly, the HOG algorithm is described and its performance profiled from a computation and bandwidth perspective. Then the IPPro soft-core processor architecture is introduced and a number of mapping strategies are covered. A HOG implementation is demonstrated on a Zynq platform, resulting in a design operating at 15.36 fps; this compares favorably with the performance and resources of hand-crafted VHDL code.



This work has been undertaken in collaboration with Heriot-Watt University in a project funded by the Engineering and Physical Science Research Council (EPSRC) through the EP/K009583/1 grant. Colm Kelly has received support from Thales Air Defence.


  1. 1.
    Woods R, McAllister J, Lightbody G and Yi Y (2017) FPGA-based Implementation of Signal Processing Systems. 2nd edn. Wiley, UK.CrossRefGoogle Scholar
  2. 2.
    Jain R, Kasturi R and Schunck B G (1995) Machine Vision. McGraw-Hill, Inc.Google Scholar
  3. 3.
    Deschamps J P, Sutter G D and Cantó E. (2012) Guide to FPGA Implementation of Arithmetic Functions. Springer.CrossRefGoogle Scholar
  4. 4.
    Xilinx Inc. (2016) System Generator for DSP. Available via Cited 29 April 2017.
  5. 5.
    MathWorks (2016) HDL Coder. Available via Cited 29 April 2017.
  6. 6.
    McKinsey and Company (2012) McKinsey on Semiconductors. Available via Cited 29 April 2017.
  7. 7.
    Xilinx Inc. (2015) DS183: Viretx-7 and XT FPGAs Data Sheet: DC and AC Switching Characteristics. Available via Cited 29 April 2017.
  8. 8.
    ARM Ltd. ARM7TDMI Technical Reference Manual (ARM DDI 0029G). Available via Cited 29 April 2017.
  9. 9.
    Xilinx Inc. (2011) LogiCORE IP Divider Generator v3.0. Available via Cited 29 April 2017.
  10. 10.
    Texas Instruments (2010) TMS3206678 Rev.E. Available via Cited 29 April 2017.
  11. 11.
    Eker J and Janneck J (2003) CAL language report. University of California at Berkeley Technical Report UCB/ERL M, (3).Google Scholar
  12. 12.
    Blair C, Robertson N M and Hume D (2013) Characterizing a Heterogeneous System for Person Detection in Video Using Histograms of Oriented Gradients: Power Versus Speed Versus Accuracy. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 3(2), 1236–247.CrossRefGoogle Scholar
  13. 13.
    Oberman S F and Flynn M (1997) Division algorithms and implementations. IEEE Transactions on Computers, 46(8), 833–854.MathSciNetCrossRefGoogle Scholar
  14. 14.
    Robertson J E (1958) A New Class of Digital Division Methods. IRE Transactions on Electronic Computers, EC-7(3), 218–222.CrossRefGoogle Scholar
  15. 15.
    Macii E, Paliouras V and Koufopavlou O (2004) Power Aware Dividers in FPGA. Proc. of Power and Timing Modeling, Optimization and Simulation, 574–584.Google Scholar
  16. 16.
    Thomas D B, Howes L and Luk W (2009) A Comparison of CPUs, GPUs, FPGAs, and Massively Parallel Processor Arrays for Random Number Generation. Proc. of ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 63–72.Google Scholar
  17. 17.
    Dalal N and Triggs B (2005) Histograms of oriented gradients for human detection. Proc. of IEEE Conference on Computer Vision and Pattern Recognition, 886–893.Google Scholar
  18. 18.
    Hahnle M, Saxen F, Hisung M, Brunsmann U and Doll K (2013) FPGA-Based Real-Time Pedestrian Detection on High-Resolution Images. Proc. of IEEE Conference on Computer Vision and Pattern Recognition, 629–635.Google Scholar
  19. 19.
    Bauer S, Brunsmann U and Schlotterbeck-Macht S (2009) FPGA Implementation of a HOG-based Pedestrian Recognition System. Proc. of IMPC-Workshop, Karlsruhe.Google Scholar
  20. 20.
    Xie S, Li Y, Jia Z and Ju L (2013) Binarization based implementation for real-time human detection. Proc. of International Conference on Field-Programmable Technology, 1–4.Google Scholar
  21. 21.
    Kadota R, Sugano H, Hiromoto M, Ochi H, Miyamoto R and Nakamura Y (2009) Hardware Architecture for HOG Feature Extraction. Proc. of International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 1330–1333.Google Scholar
  22. 22.
    Siddiqui F M, Russell M, Bardak B, Woods R and Rafferty K (2014) IPPro: FPGA based image processing processor. Proc. of IEEE Workshop on Signal Processing Systems, 1–6.Google Scholar
  23. 23.
    Kelly C, Siddiqui F M, Bardak B and Woods R (2014) Histogram of oriented gradients front end processing: an FPGA based processor approach. Proc. of IEEE Workshop on Signal Processing Systems, 1–6.Google Scholar
  24. 24.
    Negi K, Dohi K, Shibata Y and Oguri K (2011) Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm. Proc. of International Conference on Field-Programmable Technology, 1–8.Google Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2019

Authors and Affiliations

  • Colm Kelly
    • 1
  • Roger Woods
    • 2
    Email author
  • Moslem Amiri
    • 3
  • Fahad Siddiqui
    • 2
  • Karen Rafferty
    • 2
  1. 1.Thales Air DefenceBelfastUK
  2. 2.Queen’s University of BelfastBelfastUK
  3. 3.University of BristolBristolUK

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