Abstract
In this chapter, a fourth design example is presented. The implemented circuit is the Advanced Encryption Standard (AES) which is another cryptographic block. In this implementation, the static power consumption of the MCML gates is reduced by applying the Power Gated MCML (PG-MCML) technique where the current source of the gates is switched off when there is no activity. The example block is implemented by using both MCML and CMOS gates. The power consumption, area, and the DPA-resistance figures with the one of static CMOS and conventional MCML are compared. The results show that the PG-MCML library can achieve a power consumption comparable with the one of static CMOS, thus proving that PG-MCML cells can suit the strict power budget of battery operated devices.
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Badel, S., Baltaci, C., Cevrero, A., Leblebici, Y. (2019). Design Example IV: Advanced Encryption Standard (AES). In: Design Automation for Differential MOS Current-Mode Logic Circuits . Springer, Cham. https://doi.org/10.1007/978-3-319-91307-0_9
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DOI: https://doi.org/10.1007/978-3-319-91307-0_9
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