Design Example I: Low-Noise Encoder Circuit for A/D Converter

Abstract

In the previous chapters, we have presented an analysis of MCML circuits and deducted design guidelines, specifically for standard cells. We have then presented a methodology for designing MCML standard-cell libraries and a design flow for implementing MCML standard-cell based circuits. In this chapter, we will present the implementation of an MCML standard-cell library in a 0.18 μm CMOS technology, and the RTL-to-GDSII design flow. We will then present the redesign in MCML of a CMOS standard-cell based decoder circuit for an analog-to-digital converter. As part of a mixed signal circuit, this design example targets low-noise operation.