Carbon Interconnects

Abstract

This chapter provides a comprehensive review of the state of the art of carbon-based interconnects, presenting the most relevant results in modeling, fabrication, and integration.

Due to their outstanding electrical, thermal, and mechanical properties, carbon-based materials such as carbon nanotubes and graphene nanoribbons have been proposed as candidates for realizing electrical interconnects, to overcome the limits foreseen at nanoscale for conventional materials like copper. Extensive consideration has been so far devoted to this emerging interconnect technology, with a huge effort spent in theoretical and experimental works aimed at demonstrating its feasibility.

Simulation results opened the door to the promise of a real technological breakthrough, characterized by fascinating properties like electrical and thermal ballistic transport, reduced delay, insensitivity to skin effect, mitigation of electromigration, thermal stability, and enhanced reliability and resiliency. These results suggest using carbon materials to fabricate all types of interconnects for future nanoscale VLSI circuits, on-chip signal and power interconnects, through-silicon vias, chip-to-package interconnects, and so on.

In practical applications, these promising results are strictly related to the possibility of realizing high-quality carbon interconnects, with a satisfactory control over parameters like chirality, density, alignment, defects, surface roughness, and contacts. Therefore, major efforts have been made in the last years to assess reliable design approaches and effective fabrication processes. Although technological solutions have been demonstrated to solve issues like the compatibility of the growth temperature with the standard CMOS technology, the needed density and degree of alignment, the presence of defects, and the contact quality, these solutions are still not suitable for a mass production, and so the route to the industrial exploitation of this emerging technology is still long.

23.1 Interconnect Challenges for Nanoelectronics

In the last four decades, the growth of the semiconductor industries has been characterized by a continuous process of dimensional scaling of silicon technology , in order to improve the performance of integrated circuits (ICs). In this period, the popular Moore’s law [1] and the classical scaling rules (e.g., the pioneering work [2]) have been at the basis of the ITRS (International Technology Roadmap for Semiconductors , [3]) which has driven the industry targets.

Given the exponential increase in the number of transistors, a more and more crucial role has been played by the electrical interconnects, needed to manufacture high-performance microchips . A typical interconnect structure inside a silicon chip is depicted in Fig. 23.1: starting from the transistor level (local level), the signal is routed through the chip in horizontal (lines) and vertical (vias) interconnects, passing from the intermediate level and ending to the global level. Typical cross-section dimensions are reported in Table 23.1. The interconnect density is of the order of some km/cm².

Fig. 23.1

Schematic of a typical on-chip interconnect structure

Table 23.1 Dimensions of the interconnect cross section for two technology nodes (ITRS, [3])

The overall performance is strongly affected by the behavior of interconnects, which introduce power dissipation, delays, signal integrity issues, and reliability problems. All these effects worsen with dimensional scaling, and thus in the past, significant threats related to scaling were solved by replacing materials and redesigning architectures. For instance, copper (Cu) interconnects have replaced aluminum to reduce the electrical resistance and to mitigate electromigration [4]. Furthermore, the use of low-k dielectrics has lowered the capacitance [5], with the result of lowering the interconnect delay and the dynamic power dissipation. Great investments in new materials and processes and in the increase in the number of layers have allowed the continuous scaling of interconnects to comply with new technology nodes, as, for instance, the 22 nm node [3]. However, when shrinking the dimensions to nanoscale, where the lateral dimension of a Cu interconnect becomes comparable or smaller than its electron mean free path , its electrical resistivity dramatically increases [6], due to surface and grain-boundary scattering mechanisms (see Fig. 23.2). Additional problems, like reduced electromigration lifetime and poor adhesion to interlayer dielectrics, along with the limits of the present dielectrics, suggest replacing the conventional Cu/low-k technology with novel solutions with innovative materials.

Fig. 23.2

Copper resistivity versus wire width. (Reproduced from ITRS, [3])

Besides the behavior of the materials at nanoscale, another challenge for nano-interconnects is given by the architecture or, more generally, by the design itself [7]. Interconnects are used for several purposes: they can carry signals or power, data or clock, analogue or digital, and so on. An optimal design is therefore strongly related to the final purpose of the interconnect, since there are deep differences in operating conditions and required performance. A proper design for signal interconnects, for instance, must be aware of all the signal integrity issues arising from phenomena like delay, mismatch, dispersion, crosstalk, etc. [8]. This usually dictates design strategy aimed at minimizing such phenomena, by lowering the corresponding circuit parameters (e.g., coupling capacitances, resistances, loop inductance, etc.). Speaking about power interconnects, such as those used in power delivery networks (PDNs), their reliability is strongly affected by the problem of electromigration. Therefore, in designing them, a crucial parameter to take under control is the current density [9]. Indeed, the nanoscale interconnects may be required to carry on current densities of the order of MA/cm², leading to a volumetric heat production of the order of 10³–10⁴ W/mm³ [3]. Furthermore, for PDNs it is essential to get the lowest value of resistance in order to minimize unwanted effects like the voltage drop.

As a consequence of the above considerations, the interconnect structure of an IC must be designed by optimizing contemporarily many performance indicators, which is a great challenge at the nanoscale, where the scaling laws may change. For instance, nanoscale effects like those associated with quantum capacitance or kinetic inductance may break the simple scaling rules used so far to mitigate the crosstalk noise between two interconnects that are based on a proper ratio between inter-wire distance and wire diameter (e.g., [10]). Finally, in the route to the nanoscale, the semiconductor industry is also investigating radical changes in interconnect technology, such as the use of optical links [11] or RF interconnects [12].

Given these premises, it is not surprising to realize that in the last decade, many companies promoted research on emerging interconnect technologies, such as those based on carbon. Indeed, due to their outstanding physical properties, carbon-based materials are promising candidates to replace copper for nano-interconnects [13,14,15]. To this end, extensive consideration has been so far devoted to the use of carbon nanotubes (CNTs), i.e., a 1D allotrope of graphene obtained by rolling up a graphene sheet [13]. They are denoted as “single-walled” (SWCNTs) if a single sheet is considered or as “multi-walled” (MWCNTs) if composed of several nested sheets. Alternatively, interconnects made by graphene nanoribbons (GNRs) have been also investigated. Both materials exhibit low electrical resistivity, high thermal conductivity, and high current-carrying capability, besides other excellent mechanical properties [16, 17]. In fact, the electron mean free path is of the order of μm in SWCNTs [18] and in GNR [19], of tens of μm in MWCNTs [20], to be compared to the few tens of nm in Cu. The current density may reach values of 10⁹ A/cm² in CNTs [21], and of 10⁸ A/cm² in GNRs [22], whereas the maximum attainable value for Cu is about 10⁷ A/cm². As for mechanical properties, the CNTs may exhibit a Young’s modulus of about 1 TPa [23], five times the value for stainless steel. The thermal conductivity of CNTs may reach values of about 3500 Wm⁻¹ K⁻¹ [24], whereas for Cu it is usually about 400 Wm⁻¹ K⁻¹.

Given such fabulous properties, carbon-based interconnects have been widely investigated for future VLSI applications: ballistic transport means reduced resistance, hence reduced delay for signal lines. The combination of mechanical strength and large current capability mitigates the electromigration issues, a highly desirable behavior for power interconnects. High thermal conductivity results in more efficient heat dissipation, which in turns allows using such interconnects in 3D architecture and/or in nanopackaging.

However, all these outstanding values may dramatically drop when real-world interconnects are fabricated, given the necessity of using bundles of CNTs or arrays of GNRs rather than isolated specimens. Controlling the quality of such bundles (e.g., in terms of density and alignment, terminal contacts, defects, and inclusions) is among the most limiting factors for the success of such a technology, along with compatibility between the CNT and the CMOS growth processes. Despite all the above limits, the recent first examples of successful integration between CNT and CMOS technologies (e.g., [25,26,27,28,29,30]) opened the possibility for carbon interconnects to move toward real practical applications. In [25], the solder bumps for flip-chip interconnects are made by CNT bundles (Fig. 23.3); in [26] high-frequency CMOS oscillators are realized by using interconnects made by CNTs (Fig. 23.4), whereas in [27] they are wired with GNRs interconnects; in [28], CNT bundles have been used to fabricate through-silicon vias; finally, in [29] an all-CNT computer with PMOS transistors is demonstrated.

Fig. 23.3

CNT pillar bumps for flip-chip technology: (a) die attached to the carrier substrate; (b) zoom to two CNT bumps. (Reproduced from Yap et al. [25])

Fig. 23.4

High-frequency CMOS oscillators with CNT interconnects. (Reprinted with permission from Close et al. [26]. Copyright (2008) American Chemical Society)

In this chapter we review the state of the art of carbon-based interconnects, presenting the most relevant results in modeling, fabrication, and integration, coming to the most recent applications, where such interconnects were for the first time successfully integrated to CMOS technology.

23.2 Modeling Carbon Interconnects

23.2.1 A Generalized Ohm’s Law for Nanoscale Conductors

In view of designing carbon-based nano-interconnects, accurate and efficient equivalent circuit models are needed. To this end, one of three distinct approaches to electron transport modeling can be used: classical, semiclassical, and quantum.

The classical approach, with the most limited validity area, is the simplest one. For example, the Drude model of conductivity in metals considers the conducting electron as a classical particle, which moves in the electric field while encountering inelastic collisions with a randomly vibrating ion lattice. Assuming a conducting wire with longitudinal axis z, the model easily leads to the classical Ohm’s law that reads in frequency domain:

$$ {J}_z\left(z,\upomega \right)={\upsigma}_c\left(\upomega \right){E}_z\left(z,\upomega \right), $$

(23.1)

where J_z and E_z are the axial components of the current density and electric fields, respectively, whereas σ_c(ω) is e the Drude conductivity:

$$ {\upsigma}_c\left(\upomega \right)=\frac{\upsigma_0}{1+i\upomega /\upnu}, $$

(23.2)

ν being the collision frequency and σ₀ the DC value of conductivity.

However, at the nanoscale the classical approach leads to low-accuracy models, since new phenomena join to classical electromagnetic interactions, such as discrete energy spectrum of charge carriers, existence of phonons, ballistic transport and tunneling, many-body correlations, interface effects, etc. [31]. The quantum approach based on a Maxwell-Schrödinger model is the most accurate, since it rigorously describes all quantum effects: tunneling, spin-orbit, dipole-dipole, and spin-spin interactions. This approach leads to highly cumbersome simulations that cannot be carried out in the standard circuit-based simulation tools usually adopted by IC designers.

However, the quantum approach is not always strictly necessary at the nanoscale. Taking into account the realistic operation conditions for nano-interconnects in next technology nodes [3], with operating frequencies below 1 THz and low-bias conditions (fractions of volts), a semiclassical approach can be used. With this approach, the particle ensemble can be modeled as a non-ideal gas or as a fluid, undergoing quantum effects, which are taken into account by replacing the real particle mass by the corresponding effective value. Indeed, in the above operating conditions, for transverse dimensions of the order of nanometers the following conditions hold:

• (i) The cross-section characteristic dimension is electrically small, i.e., it is much smaller than the characteristic wavelength of the signals propagating along the conductor.

• (ii) The transverse component of the electrical current may be neglected.

• (iii) Only intraband transitions are considered, while interband ones are not allowed [32].

In addition, given the low-bias conditions, the typical voltage value verifies V < k_BT/e, being k_B the Boltzmann constant, T the absolute temperature, and e the electron charge. For instance, CNT-based integrated circuits have been proven to work under a supply voltage as low as 0.4 V, much lower than for conventional silicon ICs, e.g. [33]. Consequently, a linear relation may be assumed between electric field and current, which may be written as the generalized Ohm’s law in the wavenumber domain β [34, 35]:

$$ \left[1-\uppsi \left(\upomega \right){\upbeta}^2\right]{\widehat{J}}_z\left(\upbeta, \upomega \right)=\frac{\upsigma_0}{1+i\upomega /\upnu}{\widehat{E}}_z\left(\upbeta, \upomega \right), $$

(23.3)

$$ \uppsi \left(\upomega \right)=\frac{\upxi \left(\upomega \right){\mathrm{v}}_F^2}{\upnu^2{\left(1+i\upomega /\upnu \right)}^2},\kern0.5em {\upsigma}_0=\frac{2{v}_FM}{\upnu {R}_0X}, $$

(23.4)

where R₀ = 12.9 kΩ is the so-called quantum resistance, M is the number of conducting channels, v_F is the Fermi velocity, ν is the collision frequency and the quantities X, and ξ(ω) depends on the material used as conductor. For a CNT, it is X = πD and ξ(ω) = 1, (being D its diameter), whereas for a GNR it is X = πW (being W its width), with ξ(ω) expressed as in [35]. For a metallic nanowire (NW) of diameter D, it is X = π(D/2)² and ξ(ω) may be approximated as ξ(ω) ≈ (1 + 1.8iω/ν)/3(1 + iω/ν) [34].

The left-hand side of (23.3) introduces a spatial-temporal dispersion, whereas the right-hand side introduces a frequency dispersion. This means that Ohm’s law for nanoscale interconnects introduces nonlocal and long-lasting interactions. When the dispersion at the left-hand side is negligible, (23.3) is consistent with classical law (23.2), the only difference being in the values of the quantities related to quantum effects, such as the number of conducting channels M. This quantity is a measure of the number of subbands that effectively contribute to the electric conduction and plays a crucial role in the behavior of the carbon nanomaterials. Table 23.2 reports the value of M for carbon materials and copper nanowire at different transverse dimension: for carbon material the energy levels are quantized for transverse dimensions up to some hundreds of nm; hence M is always of the order of some units. For wires of conventional conducting materials like copper, there is no quantization of energy levels unless their diameters drop to the order of some tens of nm or lower [35].

Table 23.2 Estimated number of conducting channels M at 300 K, for a copper NW, GNR, and CNT, for different widths (GNR) or diameters (NW and CNT), at 300 K [35]

23.2.2 Equivalent Circuit Models for a Single Nano-interconnect

The main advantage of semiclassical models for the electron transport is the possibility to model carbon interconnects in the common frame of the transmission line (TL) model. Alternatively, field equation models have been also explored, such as those cast in terms of integral equations to be solved numerically (e.g., [36]), but of course such models are not so appealing to designers since they do not provide equivalent circuits.

The simplest configuration is depicted in Fig. 23.5, where the nano-interconnect is made by a signal conductor above a perfect conducting ground. The signal conductor can be either made by a CNT or a nanowire (NW), as in Fig. 23.5a, or by a GNR, as in Fig. 23.5b.

Fig. 23.5

A simple two-conductor nano-interconnect, with the signal conductor made by: (a) a carbon nanotube or a nanowire; (b) a graphene nanoribbon. (c) Equivalent transmission line model: inset is the unit cell

In the abovementioned operating conditions, at a given abscissa z, the distributions of surface currents and charges along the contour of a nanoscale conductor may be assumed to be uniform [36]. Thus, coupling Maxwell equations (with the charge conservation law) to the generalized Ohm’s law (23.3), the following relations hold between the electrical current I(z) and the voltage U(z), defined in terms of electrochemical potential:

$$ -\frac{\partial I(z)}{\partial z}=i\upomega {C}_tU(z),\kern0.5em -\frac{\partial U(z)}{\partial z}=\left({R}_t+i\upomega {L}_t\right)I(z), $$

(23.5)

where the electrical parameters L_t, R_t,and C_t are the per-unit-length (pul) inductance, resistance, and capacitance, respectively, defined as:

$$ {L}_t={L}_m+{L}_k,\kern0.5em {R}_t=\upnu {L}_k,\kern0.5em {C}_t^{-1}={C}_e^{-1}+{C}_q^{-1}{\left(1+\upnu /\upomega \right)}^{-1}. $$

(23.6)

Here, C_e and L_m are, respectively, the classical pul electrostatic capacitance and magnetic inductance for the guiding structure, whereas L_k and C_q are, respectively, the kinetic inductance and the quantum capacitance, given by:

$$ {L}_k=\frac{R_0}{2{v}_F}\frac{1}{M},\kern0.5em {C}_Q=\frac{1}{v_F^2}\frac{1}{L_k}. $$

(23.7)

From the physical point of view, the kinetic inductance describes the effects of the mass inertia of the conduction electrons, while the quantum capacitance is related to the quantum pressure arising from the zero-point energy of such electrons. The collision frequency may be expressed as ν = 2v_F/l_mfp, l_mfp being the electron mean free path .

Equation (23.5) represents the classical TL model for a two-conductor line, written in terms of the variables (I, U); hence the pul parameters (23.6) represent the parameters of the unit RLC cell in Fig. 23.2c. Specifically, the inductance is the series combination of the classical magnetic one and the kinetic one, and the capacitance is the series combination of the classical electrostatic one and a quantum one (independent of frequency, if ν/ω <  < 1). This circuit model was first derived for quantum wires in the pioneering work [37] and for CNTs in the early works of Burke, [38], in the frame of the Luttinger liquid theory. In the latter case, L_k and C_q were obtained for metallic single-walled CNTs, that is, in the case obtained by assuming M = 2 in (23.7). In [39], the same TL model applicable both to CNTs and conventional metallic nanowires was derived from a semiclassical transport theory based on the Boltzmann equation. The Boltzmann transport theory was also used to obtain the circuit models for SWCNTs in [40] and MWCNTs in [41]: such an approach was proven to be equivalent to a hydrodynamic model, the so-called fluid model, where the carriers are modeled as an electron cloud, [42, 43]. Finally, first-principles calculations and fitting with experimental results instead form the basis of the circuit models presented in [44] for CNTs and in [45,46,47] for GNRs.

Another possible TL model is obtained by recasting (23.5) in terms of the voltage V(z) defined from the electrical potential, instead of the electrochemical one:

$$ -\frac{\partial I(z)}{\partial z}=i\upomega {C}_tV(z),\kern0.5em -\frac{\partial V(z)}{\partial z}=\left({R}_t+i\upomega {L}_t\right)I(z), $$

(23.8)

In this case, the pul parameters (23.6) would change into [40,41,42,43]:

$$ {L}_t=\left({L}_m+{L}_k\right)/{a}_C\kern0.5em {R}_t=\upnu {L}_k/{a}_C,\kern0.5em {C}_t={C}_e,\kern0.5em {a}_C=1+\frac{C_e}{C_q\left(1+\upnu /\upomega \right)}. $$

(23.9)

However, this is usually only a theoretical difference, since in practical applications, the quantum capacitance C_q is at least one order of magnitude larger than the electrostatic one C_e, and typical values for the collision frequency ν are 10¹¹ → 10¹²: this means that for frequencies up to 1 THz, a_C ≈ 1.

According to (23.7) and (23.9), the pul resistance R_t, also known as the intrinsic resistance, may be expressed as:

$$ {R}_t=\frac{R_0}{M}\frac{1}{l_{mfp}}. $$

(23.10)

A great potential advantage of using carbon interconnects is their huge mean free path compared to conventional conductors, of the order of some tens of μm, as recalled in Sect. 23.1. This means that ballistic transport (which means R_t ≈ 0) is achievable for lengths comparable to those of local lines or vertical vias in on-chip interconnects.

The TL model for nanoscale interconnects (23.5), (23.6) is consistent with the classical TL model for a macroscopic line: indeed, for wire widths greater or equal to 100 nm, in conventional conductors like copper, the number of channels M becomes huge (as shown in Table 23.2), hence L_k <  < L_M, C_e <  < C_q, and so expressions (23.6) provide the classical TL pul parameters: L = L_m, C = C_e, and R = 1/(σ₀S_w), being S_w the wire section area.

To complete the circuit model in Fig. 23.5c, we should add two lumped resistances R_c at the terminations. Indeed, at the terminal contact surfaces between carbon and conventional metals, there is a barrier due to the mismatching between the band structures of the different materials [27]. This effect may be taken into account through a lumped resistor R_c:

$$ {R}_c=\frac{R_0}{M}+{R}_p, $$

(23.11)

where R₀ = 12.9 kΩ and R_p is a parasitic term due to the quality of the contacts. Therefore, even in the ballistic transport regime (R_t = 0) and assuming ideal contacts (R_p = 0), the minimum value of the electrical resistance for a carbon line would be R₀/M, which means 12.9 kΩ or 6.45 kΩ for a single metallic GNR or SWCNT, respectively. The huge contact resistance arising from the metal/carbon interfaces still remains a primary issue for the practical use of carbon interconnects, and thus many efforts are devoted to contact engineering, to lower such a value [48].

Another important difference between macroscopic and nanoscale interconnects is the phase velocity: in macroscopic TLs the working mode is the transverse electromagnetic (TEM) wave, with phase velocity $c=1/\sqrt{L_t{C}_t}.$ The working mode in nano-TLs is a surface wave with rather large longitudinal component and phase velocity given by the Fermi velocity ${v}_F=1/\sqrt{L_k{C}_q}$. To get an insight into this effect, let us refer to the interconnect in Fig. 23.5, assuming typical values for on-chip local level interconnect at the 14 nm node [3]: D = W = 14 nm, t = 2D and a relative permittivity of the embedding medium ε_r = 2.2.

Figure 23.6a shows the frequency behavior of the normalized phase velocity c(ω) = k₀/β(ω), k₀ being the vacuum space wavenumber. The dispersion introduced by the generalized Ohm’s law (23.3) leads to saturation in different frequency ranges. In all cases, the carbon line velocity saturates to a value that is two orders of magnitude smaller than the vacuum space velocity. This slowing effect is a well-known consequence of the role played by the kinetic inductance [33, 47]. The copper realization is not evidently affected by the quantum effects, and so its phase velocity exhibits a behavior similar to bulk copper, with saturation close to the ideal velocity. In a copper nanowire , the propagating velocity would be slowed down only for widths of the order of nanometers or fractions of nanometers, when the transverse quantization starts playing a role in reducing the conducting channels, as shown in Table 23.2. Figure 23.6b shows the dispersion for the attenuation constant α(ω), therefore providing information about the frequency dependence of the losses. The attenuation introduced by CNTs is lower than those introduced by the other two realizations and is almost constant over the considered frequency range. As expected, the attenuation introduced by the copper NW is increasing, with frequency increasing, and is generally lower than that introduced by GNRs.

Fig. 23.6

Dispersion effect for an on-chip interconnect with width equal to 14 nm: (a) normalized phase velocity; (b) attenuation constant

23.2.3 Equivalent Single Conductor (ESC) Model for Bundles

Isolated CNTs, GNRs, or NWs have been successfully used as electrodes in nanotransistors (e.g., [49, 50]), but are not suitable for fabricating nano-interconnects, given the huge value of the resistance introduced, and also for the presence of the contact resistance. Therefore, realistic carbon interconnects are fabricated by putting in parallel a consistent number of CNTs or GNRs, to lower such a resistance. Typical geometries for CNT interconnects are sketched in Fig. 23.7, where vertical (vias) or horizontal (lines) interconnects are supposed to be realized by bundles of SWCNTs, MWCNTs, or mixed CNTs. Horizontal lines can be also realized by means of multilayered graphene nanoribbons (MLGNRs).

Fig. 23.7

Carbon on-chip interconnects: (a) vertical vias realized with CNT bundles; (b) horizontal traces realized with CNT bundles or GNR stacks

The rigorous way to model a bundle of N CNTs or a stack of N GNRs is the generalization of (23.5) or (23.8) to the case of a multiconductor transmission line (MTL). Such equations would relate the vectors of voltages and currents through per-unit-length matrix parameters, given by (formulation 23.5):

$$ {\mathbf{L}}_t={\mathbf{L}}_m+{\mathbf{L}}_k,\kern0.5em {\mathbf{R}}_t=\upnu {\mathbf{L}}_k,\kern0.5em {\mathbf{C}}_t^{-1}={\mathbf{C}}_e^{-1}+{\mathbf{C}}_q^{-1}{\left(1+\upnu /\upomega \right)}^{-1}. $$

(23.12)

or (formulation 23.8):

$$ {\mathbf{L}}_t=\left({\mathbf{L}}_m+{\mathbf{L}}_k\right){\boldsymbol{\upalpha}}_c^{-1},\kern0.5em {\mathbf{R}}_t={\boldsymbol{\upnu} \mathbf{L}}_k{\boldsymbol{\upalpha}}_c^{-1},\kern0.5em {\mathbf{C}}_t={\mathbf{C}}_e,\kern0.5em {\boldsymbol{\upalpha}}_c^{-1}=\mathbf{I}+{\mathbf{C}}_e{\mathbf{C}}_q^{-1}{\left(1+\upnu /\upomega \right)}^{-1}. $$

(23.13)

In (23.12), (23.13), I is the identity matrix, and L_k, ν, and C_q are diagonal matrices given by:

$$ \nu =\mathit{\operatorname{diag}}\left({\upnu}_n\right),\kern1em {L}_k=\mathit{\operatorname{diag}}\left({L}_{kn}\right),\kern1em {C}_q=\mathit{\operatorname{diag}}\left({C}_{qn}\right),\kern1.25em n=1..N. $$

(23.14)

The distributed terms (23.12) or (23.13) must be augmented with the terminal contact resistances for each conductor, as in Fig. 23.5c.

The above model includes the electromagnetic interactions between CNTs and GNRs, described by the off-diagonal terms of the magnetic inductance and electrostatic capacitance matrices, but neglect the inter-bundle quantum interactions.

Indeed, moving from isolated to bundles or arrays of carbon interconnects, additional effects into the electrodynamic models should be taken into account, which leads to the deformation of the energy bands for a CNT (a GNR) in a bundle (array). This deformation can, in principle, change the quantum parameters v_n, L_kn, and C_qn of the n-th CNT (GNR), with respect to the case where it is isolated. The main physical phenomenon is the tunneling between adjacent CNT shells or adjacent GNR layers, which gives rise to a transverse electron current and strongly affects the longitudinal electron transport [51, 52]. In particular, this effect would reduce the mean free path , with respect to the values observed for isolated CNTs or GNRs. The tunneling has a great influence on the propagation characteristics when considering antisymmetric current distributions between the shells and the ribbons [51, 52] or when investigating the THz range, where it generates additional resonances or antiresonances [53]. However, for frequencies up to 1 THz, assuming all the CNTs or GNRs are fed in parallel, we can disregard this tunneling effect [53]; hence in (23.14) we can use the quantum parameters evaluated for isolated CNTs or GNRs.

Since the CNTs or GNRs are fed in parallel, an equivalent single conductor (ESC) model may be derived (e.g., [54, 55]), recasting the above MTL model into a single TL one, relating the voltage V_b(z) = V_n(z), n = 1. N, to the total current ${I}_b(z)={\sum}_{n=1}^N{I}_n(z).$

An approximated ESC model may be used in cases when the kinetic inductance (quantum capacitance) matrix dominates over the magnetic inductance (electrical capacitance), and the operating frequencies are such that ${\boldsymbol{\upalpha}}_c^{-1}\approx \mathbf{I}$. In such a case, it is:

$$ {L}_{esc}={\left({\sum}_{n=1}^N{L}_{kn}^{-1}\right)}^{-1},\kern0.5em {R}_{esc}={\left({\sum}_{n=1}^N{\nu}_n{L}_{kn}^{-1}\right)}^{-1},\kern0.5em {C}_{esc}={C}_{eb}, $$

(23.15)

where v_n, and L_kn are the quantum parameters for the n-th isolated CNT (GNR). For carbon interconnects of practical use, densely packed bundles (arrays) are to be considered; hence the equivalent capacitance C_eb can be approximated by the classical electrostatic capacitance obtained for the given bundle (array), assuming the signal trace to be a bulk conductor [56]. Furthermore, the effects of the quantum capacitances are completely hidden by the electrical capacitance.

For instance, for a bundle of SWCNTs with diameter D, at a distance t from the ground (see Fig. 23.5a), the ESC model (23.15) reduces to:

$$ {L}_{esc}=\frac{1}{N}\frac{3{R}_0}{4{v}_F},\kern0.5em {R}_{esc}=\upnu {L}_{esc},\kern0.5em {C}_{esc}=2\uppi \upvarepsilon /\ln \left(\frac{2t}{D}\right). $$

(23.16)

In (23.16) only one-third of CNTs in the bundle are assumed to be metallic, which is a realistic statistical distribution.

23.2.4 Electrothermal Models for Carbon Interconnects

Designing reliable interconnects requires a self-consistent electrothermal co-simulation in order to correctly estimate the effects of temperature change on signal and power integrity [57]. Indeed, the power dissipation induces elevated temperatures, which directly impact on the interconnect RLC parameters, since the material properties such as electrical resistivity are temperature dependent. Such effects become more critical with advanced technologies, like the technology nodes beyond 14 nm, or for three-dimensional (3D) integration technology, since they require increased power density while exhibiting greater thermal resistances. The situation is particularly critical for power interconnects, characterized by high-density unidirectional currents, which introduce electromigration and limit the current-carrying capacity of switching circuits to the overall detriment of the interconnect reliability. As pointed out in Sect. 23.1, the use of CNTs could be also desirable to alleviate electromigration issues and improve their resiliency.

An accurate electrothermal model is obtained by coupling the electrical model to the thermal model describing the heat diffusion. In the general case, the thermal model is described by a second-order parabolic partial differential equation where the unknown is a nonuniform temperature profile and the source term is a nonlinear combination of electrical variables. Indeed, the source term is mainly given by the power dissipation due to the switching activity of the devices embedded in the substrate, with an additional contribution given by the Joule heating in the interconnects. The problems are then coupled via the temperature-dependent electrical resistivity of the conductors. The solution of the electrothermal problem in the general case requires a full 3D numerical simulation of the thermal problem (via FD, FEM, or BEM methods, for instance), coupled to a circuit simulation of the electrical network, usually in a relaxation approach (e.g., [57]).

A simple electrothermal model can be obtained by assuming 1D heat flux, i.e., the heat is mainly propagating along the interconnects and the heat exchange at the boundary between conductors and insulating dielectrics is negligible. A typical arrangement is depicted in Fig. 23.5, which shows the section and lateral views of an on-chip interconnect between two metal layers, with both horizontal and vertical interconnects.

Assuming steady-state conditions, the spatial distribution of temperature along an interconnect is governed by the heat equation:

$$ \frac{d^2T(z)}{dz^2}-\frac{T(z)}{L_H^2}=-\frac{q(z)}{k}, $$

(23.17)

where q(z)is the production term, k is the thermal conductivity of the conductor, and L_H is the thermal heating length.

The thermal conductivity for a carbon nano-interconnect usually has two components, associated with electrons and phonons, respectively, ${k}^{-1}={k}_{el}^{-1}+{k}_{ph}^{-1}.$ These two terms depend in different ways on temperature and size: in the simple case of isolated metallic SWCNT of length l, the following approximation holds [58]:

$$ k\left(l,T\right)={\left(3.7\cdot {10}^{-7}T+9.7\cdot {10}^{-10}{T}^2+9.3\left(1+0.5/l\right){T}^{-2}\right)}^{-1},\kern0.5em \left(l\kern0.28em \mathrm{is}\kern0.34em \mathrm{in}\kern0.28em \upmu \mathrm{m}\right). $$

(23.18)

In a more general case, the thermal conductivity of CNTs spans a very wide range of values from some tens to thousands of W/mK, as shown in Fig. 23.8, which shows the measured value of k for single and bundled MWCNTs [59].

Fig. 23.8

Measured thermal conductivity: isolated MWCNT with D = 14 nm (solid line); bundle of MWCNTs, with D = 80 nm (broken line), and D = 200 nm (dotted line). (Reprinted figure with permission from Kim et al. [59]. Copyright (2001) by the American Physical Society)

Just like the electrical contact resistance (23.11), an important role can be played by the interface thermal resistance between CNT and metal electrodes (the so-called Kapitza resistance). Using an effective medium approach, an equivalent thermal resistance can be introduced, to include the effect of such an additional contribution. However, this contact thermal resistance may be neglected if the quality of the interface is improved, for instance, by introducing strong chemical bonds, as shown in [60].

The coupling with the electrical problem is given in (23.17) by the production term q(z), which in turn is related to the power dissipated for device activity (≈I₀V_dd, if I₀ is the device current and V_dd the bias) and to volumetric heat generated by Joule effect, q = J²ρ, being J the current density and ρ the electrical resistivity. The operating current and bias voltage of the devices can be considered independent of temperature; hence the only temperature-dependent parameter is ρ and consequently the resistance. According to (23.10), (23.11), the resistance depends on the number of conducting channels M and on the mean free path l_mfp: both parameters depend on temperature. The mean free path in CNTs is related to acoustic phonon scattering and optical scattering, ${l}_{mfp}^{-1}={l}_{mfp, ac}^{-1}+{l}_{mfp, opt}^{-1}.$ [58]. The term l_{mfp, ac} is proportional to 1/T, and l_{mfp, opt}is a decreasing function as T increases, too. In addition, l_mfp is proportional to the CNT diameter D [47]. In the temperature range [300–600 K], the following approximation formula may be used [56] that fits the data provided in [58] and the simulations given in [44]:

$$ {l}_{mfp}=D{\left[{k}_1+{k}_2T+{k}_3{T}^2\right]}^{-1}, $$

(23.19)

where k₁ = 3.01·10⁻³, k₂ = −2.12·10⁻⁵ K⁻¹, and k₃ = 4.70·10⁻⁸ K⁻².

For GNRs, the scattering comes from defects and acoustic and edge phonons [45]; hence the mean free path may be expressed as ${l}_{mfp}^{-1}={l}_{mfp,D}^{-1}+{l}_{mfp, AC}^{-1}.$ The mfp related to defects l_{mfp, D} is quite insensitive to the GNR size and temperature, and its value ranges from 0.4 to 1 μm, where the minimum is attained when strong interlayer hopping mechanism is considered. The mfp related to acoustic phonons may be expressed as [56]:

$$ {l}_{mfp, AC}=\upgamma W/T, $$

(23.20)

with the coefficient γ ≈ 9.92 ⋅ 10⁴ K. Finally, a contribution due to the edges should be taken into account, which strongly depends on the edge diffusivity and the Fermi level. This contribution can be neglected, assuming the edges to be fully specular [45]. This leads to an underestimation of the total mfp and hence of the GNR performance.

As for the number of conducting channels M, it depends on the CNT or GNR size, chirality, and temperature. In particular, M is increasing with T, according to the approximate linear piecewise formula [44, 45, 56, 61]:

$$ M\left(X;T\right)\cong \left\{\begin{array}{l}{M}_0\kern4em \mathrm{for}\ X<{x}_0/T\\ {}{a}_1 XT+{a}_2\kern1em \mathrm{for}\ X\ge {x}_0/T\end{array}\right.. $$

(23.21)

where X is the GNR width W or the CNT circumference πD, and the fitting coefficients are given in Table 23.3. Therefore, the increase of M can counteract the decrease of l_mfp, leading to cases where a negative derivative of the electrical resistance with respect to T is found. Experimental evidences of this extremely favorable behavior are reported in [62] for GNRs and in [63] for MWCNTs. Further details on this behavior are discussed in paragraph 4.3.

Table 23.3 Fitting coefficients for the number of conducting channels M in (23.17)

23.3 Challenges for Fabrication and Integration of Carbon Interconnects

The effective use of carbon interconnects in future VLSI technology will be enabled only by an efficient and compatible fabrication process, able to match the following main requirements:

• (i) It has to be cheap, reliable, and easily scalable, in view of its industrialization.

• (ii) The resulting intrinsic and contact resistances of the carbon interconnects must be kept to enough low values.

• (iii) The growth temperature must be compatible with the CMOS integration in the back end of line (BEOL).

As for point (i), the best solution would be given by a monolithic CMOS-carbon interconnect integration process. However, the state of the art is still far from this achievement, due to major problems mainly related to material limitations and temperature issues. Therefore, the existing examples of circuits where CMOS were integrated with carbon interconnects have been realized by using transfer techniques: the CNT or GNR interconnects are grown at high temperature on a suitable substrate, and then they are transferred to the final substrate, with a nanoscale manipulation controlled by atomic force and/or scanning electron microscopes [64]. Several methods have been proposed to optimize the transfer techniques, such as dielectrophoresis, used to integrate CNT [26] and GNR [27] interconnects with CMOS in ICs operating up to GHz frequencies; see Fig. 23.4. Although optimized, the transfer technique ends up being too complicated and is hence characterized by too high costs and too low yields that make it unsuitable for mass production.

Requirement (ii) is strictly related to the achievable density of the CNT bundles or GNR stacks. As pointed out in Sect. 23.2, the main limiting factor for carbon interconnects is their resistance, both intrinsic (23.10) and contact (23.11). When dealing with short interconnects like vias, their typical length may be shorter than the mean free path; thus the performance is dictated by the contact resistance. On the contrary, the lengths of the horizontal traces are typically much longer than the mean free path , so for reasonable quality carbon/metal interfaces, the contact resistance can be neglected. In any case, the only way to reduce the resistance is to improve the quality of carbon/metal contacts and to increase the density of CNTs in bundles or GNRs in arrays, and this possibility is strictly related to the fabrication technology. According to the ITRS [3], the metallic SWCNT density required to be competitive with copper in terms of resistivity must be larger than 10¹³ cm^‐2. Assuming all aligned and ideally close-packed SWCNTs, the maximum achievable density is about 2 ⋅ 10¹⁴ cm^‐2, obtained with SWCNTs with 0.4 nm diameter [65]. However, in a random distribution of SWCNTs, only 1/3 are metallic. In addition, in real bundles it is extremely hard to match the above ideal conditions. The metallic fraction may be increased by using MWCNTs, since in that case the semiconducting shells can also contribute to the electric conduction. However, to this end the inner shells must be opened to contact with electrodes [66].

As for point (iii), the compatibility with standard CMOS technology requires a process temperature that must be lower than 400 °C. Unfortunately, as shown later, the fabrication techniques suitable for a mass production of CNTs or GNRs are characterized by higher temperatures, and the possibility of lowering them has a major drawback in the increase of defects and so in the decrease of the quality of the carbon interconnect.

Summarizing, contact quality, bundle density, process temperature, and alignment [67, 68] are the main aspects to be taken into account to obtain an effective fabrication process for carbon interconnects.

23.3.1 Fabrication of Carbon Nanotube Interconnects

The fabrication of CNTs can be effectively done by means of three main techniques: arc discharge, laser vaporization, and chemical vapor deposition. The arc discharge method, based on the evaporation of graphite electrodes in electric arcs (used by Iijima to synthesize the first CNT [69]), provides high crystalline quality but requires too high temperature (about 4000 °C) and introduces a high level of impurity [70]. On the other hand, the laser vaporization method, based on the laser-assisted evaporation of high-purity graphite, provides high level of purity, but it is limited by a modest yield, not suitable for mass production [71]. As for now, the most promising technique is chemical vapor deposition (CVD) or its derivatives such as plasma-enhanced CVD (PECVD) and hot-filament CVD (HFCVD). The advantages of such techniques reside in a selective growth of aligned CNTs and in their scalability [72, 73] that is essential in view of mass production.

In order to grow a CNT interconnect on a silicon or other substrates by CVD, a catalyst metal, such as iron (Fe) or cobalt (Co) is needed (the diameters of CNTs will almost correspond to the size of the metal catalyst islands). The growth mechanism is schematically reported in Fig. 23.9 [74]: the substrate is heated, and a carbon source gas is supplied, for instance, methane (CH₄), ethylene (C₂H₄), or acetylene (C₂H₂). The gas molecules decompose at the metal surface, then the carbon slops down through the metal, and the CNTs grow up across the metal bottom, pushing up the metal particle. Until the metal top is in contact with the gas and the excess carbon does not fully cover it, such a mechanism continues to grow the CNT longer and longer.

Fig. 23.9

Mechanism for CNT growth with chemical vapor deposition . (Reproduced from Kumar [74])

The quality of a bundle of single-walled or multi-walled carbon nanotubes is mainly related to the density, the absence of defects, the alignment, and the percentage of metallic tubes, all of which strongly influence the number of conducting channels, as pointed out in Sect. 23.2. By using the CVD method, the CNT density is strongly related to the size of the catalytic particles, which is in the order of nanometers. The density may be improved by reducing the catalyst nanoparticle size, which in turns leads to a reduction of the CNT diameter. The factors that limit such a reduction are given by the unwanted particle aggregation and by the interaction between the particle and the substrate. To this end, insulating substrates outperform metallic ones. The simultaneous control of the particle size and the substrate surface is difficult, and thus the maximum density achieved with standard CVD techniques is about 10¹² cm^‐2, one order of magnitude less than the targeted value [71]. However, the desired values of density may be obtained by means of costly improvement techniques, such as the use of cyclic deposition and annealing of the catalyst (achieving densities of about 10¹³ cm⁻² [75], see Fig. 23.10), the use of refractory conductive films to limit the catalyst diffusion into the support (achieving densities of about 5⋅10¹² cm⁻² [76]), or the use of nucleation and growth by sputtering (achieving densities of about 1.2⋅10¹³ cm⁻² [77]).

Fig. 23.10

A high-density CNT forest grown on a metallic support. (Reprinted with permission from Esconjauregui et al. [75]. Copyright (2010) American Chemical Society)

As previously pointed out, a major issue for CNT/CMOS integration is the compatibility of the CNT growth temperature with typical VLSI technology temperatures. Indeed, growth occurs at temperatures between 550 and 1000 °C using classical CVD techniques, whereas CMOS compatibility requires a maximum temperature of 400 °C. An efficient technique to lower the temperature is remote plasma CVD , where the plasma is generated far away from the substrate: in [78], MWCNT vias have been fabricated at 390 °C, whereas in [79] the synthesis of CNT bundles at 400 °C has been reported. An alternative technique is thermal CVD, based on the lower activation energy of catalysts: by means of such a technique, temperatures as low as 350 °C have been achieved in [80]. The main limiting factor in lowering the temperature with the above methods is the increase of undesired defects of the CNT structure, due to the poor diffusion of the carbon atoms placed close to the edges. Indeed, by means of PECVD , it is possible to lower the temperature to 120 °C, as demonstrated in [81], but with very low-quality CNTs.

Another important feature to control in view of fabricating good quality CNT bundles is the alignment of the tubes, which strongly impacts the electrical and thermal properties of the interconnect. Indeed, all the abovementioned techniques for mass production of CNTs lead to randomly oriented tubes in the bundles, and thus their alignment must be externally imposed. Two main approaches may be followed: the alignment can be imposed during the growth or post-growth, respectively. CNT alignment during the synthesis is obtained by placing nanoparticles of a metal catalyst on the substrate, exploiting the attitude of CNTs of growing on such particles in the normal direction with respect to the substrate. Unwanted bending may be avoided by increasing the density of catalysts, whose activity may be efficiently enhanced by the presence of water [82]. The process may be further enhanced by applying an external electrical field during the growth [83, 84]. Although this approach is easy to implement, its limit resides in the presence of metal catalyst particles in the final CNT bundle. Several post-growth techniques have been proposed, which are in general more cumbersome, but result in cleaner and well-dispersed CNTs [85]. Such techniques start with isolating the CNTs through dispersion and centrifugation with a dispersant (e.g., a polymer or surfactant). The alignment is then realized by means of the action of external forces, related to electrical and magnetic fields. In view of industrial production, techniques like those based on gas flow are found to be suitable, given their scalability [86].

The last issue to be considered is the role of the contact resistance that appears at any CNT/metal interface, since its huge value (in the order of kΩ per single tube) is one of the major limiting factors in the use of the nano-carbon interconnects. This is especially true for local interconnects, since in this case the main contribution to the overall resistance comes from the lumped term (23.11), rather than from the intrinsic distributed one (23.10). As pointed out in (23.11), the contact resistance is given by a quantum term that represents a bulk value and another term that depends on the quality of the contacts. The main problem is related to the small contact area between CNTs and metal electrodes that makes the electrical coupling between them difficult. Understanding the coupling mechanisms at the interface, both physical and chemical, is essential to effectively reduce the contact resistance. The most popular contact geometries are the so-called side contact and end contact; see Fig. 23.11. The side contact may be realized by drop-casting on electrodes the CNTs suspended in alcohol. The end contact is usually realized by bonding the metal surface atoms effectively to unsaturated C-bonds at the edge of the CNT shell. The two contacts lead to contact resistance values in the range of kΩ per single tube. To further reduce such values, several techniques are proposed, such as the use of Joule heating to induce annealing at the interface or the improvement of the wetting and of the formation of chemical bonding, for instance, by interposing a graphitic interfacial layer between CNTs and metal, as shown in [87] for a side-contacted CNT-based field-effect transistor. A comprehensive review of the results so far obtained for side and end contacts may be found in [48]. However, while the methods mentioned above are effective for isolated CNTs, they are not so effective for bundles since they are not suitable for scaling up. To improve the contact with CNT bundles, chemical-mechanical planarization is proposed, with a proper selection of the electrode material [88], or the use of an end-bonded geometry with a metallization process, as shown in [89]. A further improvement has been obtained by moving to the so-called “all-around” geometry, where the contacts occur both at the tip and at the side of the bundle [90]. Despite all these improvements, the contact resistance is still so high that the electrical resistivity of CNT bundle interconnects obtained so far falls, in the best cases, in the range 10⁻²–10⁻³ Ωcm, about three orders of magnitude higher than for nanoscale copper.

Fig. 23.11

Two different types of metal/CNT contact: (a) end contact; (b) side contact

23.3.2 Fabrication of Graphene Interconnects

The most popular solution for graphene interconnects is the use of single or stacked graphene nanoribbons that can be fabricated with several techniques, either based on lithographic or catalytic cutting, on epitaxial methods, or on chemical assembly [91]. Indeed, GNRs have been fabricated, for instance, by means of direct CVD on metal substrates [92], of epitaxial growth on silicon carbide wafers [93], of top-down plasma etching, Fig. 23.12 [94], of exfoliation techniques [95], of on-surface polymerization with suitable molecular precursor, Fig. 23.13 [96], or by unzipping CNTs via oxidation [97].

Fig. 23.12

Fabrication of graphene nanoribbons via top-down etching

Fig. 23.13

STM image of graphene nanoribbons of different lengths obtained with a fabrication technique based on-surface polymerization. (Reproduced from Kimouche et al. [96])

The main challenge in fabricating GNRs is the requirement for high-quality graphene at the wafer-scale and for suitable substrates for patterning interconnect widths usually in the order of few nanometers. The choice of fabrication method and of the supporting substrate strongly influences the final performance of the interconnect: for instance, the conductivity of a GNR on a substrate may decrease orders of magnitude with respect to that of the same GNR suspended, because of the trapping effect of the substrate on the electrical charges. Indeed, mean-free-path values of about 1 μm have been reported for suspended GNRs, whereas when they lie on SiO₂ substrate, such a value reduces to few tens of nm, comparable to that of the copper; see Fig. 23.14 [98]. Another major issue is given by the edge effects: rough edges and dangling bonds dramatically reduce the electrical properties of GNRs, because of the modification of the band structure. For this reason, if the GNR is too narrow (below 60 nm), it always behaves as a semiconductor, with a bandgap inversely proportional to its width and with strongly reduced mobility [98]. The edge scattering is therefore one of the most limiting factors for scaling down the minimum size of GNR interconnects. Finally, the fabrication method is also responsible for the final amount of defects and impurities, which is another fundamental aspect to be controlled, since it introduces additional degradation mechanisms such as Coulomb scattering.

Fig. 23.14

Electron mean-free-path values of GNRs versus their widths, for suspended (“bulk”) GNRs (1.2 μm line) and for GNRs on substrates. (Reprinted with permission from Rakheja et al. [98]. Copyright (2013) IEEE)

Although many of the fabrication methods cited provide high-quality graphene on silicon substrates, such as the mechanical exfoliation, unfortunately they are unsuitable for mass production and incompatible with CMOS technology requirements. For instance, the silicon sublimation method is a promising technique able to control few layer graphene, but the requested annealing temperature is too high for CMOS compatibility. Therefore, as far as now, the most promising technique is again based on chemical vapor deposition (CVD process, as in the case of CNT interconnects (see Sect. 23.3.1)). The GNRs are grown via CVD at ambient pressure on a substrate such as nickel or copper. After the CVD growth, the graphene ribbons are transferred to the final substrate chosen for the envisaged application, via an etching process, as shown, for instance, in Fig. 23.15 where the fabrication of a GNR-based FET is shown [99]. First, graphene is grown at 1000 °C by using CVD on a copper layer and is then transferred to the final substrate. In detail, after the GNR growth, a layer of polymethyl methacrylate (PMMA) is spin-coated on top of the substrate, in order to lift off the GNR from it and to transfer to the target substrate, Fig. 23.15a. Next, the electrodes may be fabricated by depositing them by an electron-beam evaporation system, as shown in Fig. 23.15b. GNR arrays of different widths can be further fabricated using electron-beam lithography, Fig. 23.15c. Subsequently, oxygen plasma and chemical washing are used to remove the excess graphene to form nanoribbons (Fig. 23.15d) and excess PMMA (Fig. 23.15e), respectively.

Fig. 23.15

CVD-based fabrication of a GNR interconnect and its transfer to the target substrate. (a) transfer of CVD graphene onto substrates; (b) graphene patterning and contact metal deposition; (c) graphenenanoribbon patterning; (d) graphene etching; (e) final GNR array. (Reprinted with permission from Tan et al. [99]. Copyright (2013) American Chemical Society)

This method is in principle suitable for industrial production, since it can be scaled to transferring large areas of graphene from arbitrary substrates to CMOS substrates. However, the transfer step is critical, being responsible for the final quality of the device in terms of the presence of defects and impurities [100]. Enhanced techniques may be adopted to preserve the smoothness of the GNR edges, such as the use of a gas-phase etching [101].

Other promising fabrication approaches are based on bottom-up techniques, such as controlled unwrapping of oxidized carbon nanotubes by means of sonication [97], or the use of 1D chains of carbon precursors [102]. The structure of the precursor may be tailored to obtain a good control over the GNR width and good edge smoothing. The present limits for the bottom-up approaches reside in their low applicability to substrates of interest for interconnects, such as Si or SiC, although some examples of self-growth on SiC substrate have been demonstrated [103]. An alternative bottom-up fabrication technique for graphene-based interconnects has been recently proposed in [104], where a low-cost fabrication of graphene flakes has been presented based on thermal expansion of intercalated graphite, and an interconnect on FR4 dielectric has been fabricated by a drop-cast technique. The interconnect has been created by self-assembly of graphene flakes, under the action of an external electric field.

As for carbon nanotubes, a single monolayer graphene nanoribbon cannot be used as an interconnect due to the huge value of the contact resistance, so a configuration of practical use must exhibit a high number of GNRs fed in parallel in order to reduce the overall resistance. The most suitable solution, therefore, is that of using multilayer GNRs (MLGNRs) instead of monolayers.

As for the CNT bundles in Sect. 23.2, the MLGNR interconnects may be linked to the outer world through side or top contacts: in the first case, all GNR layers are physically connected to contacts, while in the second one, only the topmost layer is connected to the contacts. For this reason, top-contacted MLGNRs usually exhibit worse performance, although they are easier to fabricate. Anyway, simulations and experimental results on both top- and side-contacted MLGNRs have demonstrated that, with suitable doping, such interconnects may outperform copper ones, for instance, in terms of electrical resistance [105]. Indeed, stacking graphene monolayers at the van der Waals distance may lead to a structure similar to that of graphite, whose electrical properties are much worse than those of graphene due to interactions between layers. Intercalating doping molecules between the layers allows them to be electrically decoupled , so that N-stacked GNRs may behave as N parallel independent channels for electrical transport. In [106] a CVD synthesized MLGNR interconnect with FeCl₃ intercalation doping has been presented that matches copper resistivity at 20 nm width, Fig. 23.16. Furthermore, the width-dependent doping effect due to increasingly efficient FeCl₃ diffusion in scaled MLGNRs suggests that this interconnect may outperform Cu for sub-20 nm widths. A different dopant that has been considered is lithium, which has been shown to improve the conductivity by more than a factor of ten [107].

Fig. 23.16

An intercalation-doped multilayer graphene nanoribbon interconnect and the achieved values of resistivity compared to a copper interconnect vs wire widths. (Reprinted with permission from Jiang et al. [106]. Copyright (2016) American Chemical Society)

From a fabrication point of view, a challenging task is the control of the uniformity of doping on the GNR surface and at the interface with the substrate. A nonuniform accumulation of dopants close to the substrate leads to a screening effect of the innermost GNR layers, hence to their different contributions to the conduction, compared to the layers that are located far from substrate. A possible solution to this problem is the shift of the Fermi energy level of the upper layers.

23.4 Performance Analysis of Carbon Interconnects

Given their promising features, carbon materials such as carbon nanotubes and graphene nanoribbons have been included from almost a decade ago among the innovative materials for next-generation interconnects by the ITRS [3]. However, given the major issues of compatibility between their fabrication conditions and those of the standard CMOS technology discussed in Sect. 23.3, few examples of practical realizations of electronic circuits integrating carbon interconnects are so far available, such as those reported in Sect. 23.1. Therefore, many of the results related to the performance analysis of carbon interconnects are still based on simulation of models, although more and more accurate, that have been proposed in the last decade [108].

As a general result, it has been shown that, despite their huge contact resistance values, CNT and GNR interconnects may be arranged in such a way to be competitive or even better than copper ones for on-chip interconnects either at the local and at the global level [47, 108,109,110,111]. Carbon nanotube vias may also outperform copper ones, and their use has been largely investigated either as classical on-chip vias [112] and as through-silicon vias (TSVs), in the so-called 3D integration schemes [113,114,115, 116]. Promising results are also foreseen for carbon-based power interconnects in the chip power delivery networks [108, 117] and for the chip-to-package carbon interconnects such as pillar bumps [25].

Table 23.4, extracted from table INTC9 in [3], summarizes the current status for the use of carbon materials as interconnects, either considered as an alternative to copper or as native device interconnects.

Table 23.4 Advantages and issues for carbon interconnects [3]

23.4.1 On-Chip Interconnects

On-chip interconnects are characterized by three main hierarchical levels, local, intermediate, and global, moving from the substrate to the package. Typical dimensions change from level to level and with the technology node considered: Table 23.1 reports the typical values of the cross-section dimensions for interconnects for two technology nodes, taken from [3]. Typical arrangements for on-chip interconnects are shown in Fig. 23.7, where they are made of bundles of CNTs or of multilayer GNRs.

Taking into account the considerations given in Sect. 23.2, if we assume well-aligned CNTs or GNR layers, without defects or irregular edges, the main aspects affecting their performance are the chirality, the density, and the contact resistance.

As for the chirality, statistically in a population of CNTs or GNRs, one-third of the population is metallic and two-third semiconducting. It is possible to increase the fraction of metallic samples, but this would increase the cost of their production. This statistic has a different impact on the different types of carbon materials: for instance, a semiconducting single-walled CNT does not contribute to the conductivity (see Table 23.3, M = 0), whereas in multi-walled CNTs, a significant contribution to the number of conducting channels can also come from semiconducting shells, depending on their diameter. Therefore, for a given cross section, the use of SWCNTs instead of MWCNTs leads to bundles with larger numbers of CNTs but with only one-third active in the electrical conduction. The choice is then related to this trade-off, along with the possibility to increase the density, i.e., to maximize the area occupied by CNTs in the bundle (filling factor). Note that putting the CNTs too close together to maximize density leads to unwanted inter-CNT interactions that result in a degradation of the electrical performance. The same happens, as pointed out in Sect. 23.3, when GNR layers are put at the minimum distance (van der Waals distance, about 0.34 nm) : this condition maximizes the density, but the strong interlayer interactions lower the conductivity of the structure to values similar to graphite rather than graphene. Finally, a crucial parameter to be taken into account for performance analysis is the contact resistance, whose role has been discussed in Sect. 23.3.

Many efforts have been devoted in the recent literature to carry out a performance analysis for on-chip carbon interconnects. In particular, many works compare such interconnects to conventional ones, based on simulation results. The adopted models have been refined and improved in these years to include the realistic effects expected from the fabrication limits, as discussed in Sect. 23.3 [46, 47, 98, 108,109,110,111].

A parameter of major interest for an electrical interconnect is of course its electrical resistance or equivalently its electrical resistivity that must be as low as possible (ideally equal to zero), in order to mitigate issues like energy losses, signal delay, and Joule heating. The electrical resistance of a CNT interconnect has been predicted to be competitive with that of copper, at any hierarchical level of an integrated circuit, provided that high enough densities and low enough contact resistances are obtained. As an example, Fig. 23.17 shows the DC electrical resistivity at room temperature obtained by assuming the resistance model (23.9)–(23.11), comparing CNT and copper interconnects at various hierarchical levels and for two different technology nodes. Here we assume a filling factor of 80% and a value for the parasitic resistance of 50 kΩ for each conduction channel. As shown, CNT interconnects exhibit lower resistivity from a given value of the line length on. For shorter length, the result is dominated by the huge values of the contact resistance. Of course, lowering the parasitic resistance would lead to a lower value for this transition length. The result is also dependent on the bundle density that must be high enough. Indeed, Table 23.5 reports the minimum density of metallic SWCNTs required to obtain the same resistivity as Cu interconnects, for the several technology nodes foreseen by the ITRS for the future.

Fig. 23.17

Electrical resistivity values predicted for Cu and CNT on-chip interconnects versus the line length, for (a) 14 nm node, local level; (b) 14 nm node, global level; (c) 22 nm node, local level; (d) 22 nm node, global level

Table 23.5 Minimum density of SWCNT interconnects to be competitive with copper ones

Another design parameter to be optimized is the CNT diameter that directly impacts the number of channels M (23.21) and hence the resistivity. A larger diameter means a higher value for M, but a smaller number of tubes for a given interconnect cross section. The impact of diameter is different from SWCNTs and MWCNTs due to the different role of the semiconducting shells in the electrical conductions; therefore a trade-off solution must be found case by case between the diameter of single CNT and density in the bundle.

As for GNR interconnects, their resistivity is usually worse than that of copper ones, as shown in Fig. 23.18, taken from [98]. The figure shows the per-unit-length electrical resistance values versus the line width, e.g., the technology node, comparing different realizations of GNR lines with Cu. In particular, different values of the edge-scattering coefficient P_GNR, the Fermi level E_f, and the substrate-limited mean free path λ_SUB are considered. As a general result, GNR resistance will become comparable to or even lower than Cu only for future technology nodes, with widths lower than 6–7 nm, only assuming smooth edges and low Fermi levels and no additional scattering from the substrate. As pointed out in Sect. 23.2, for GNR interconnects to be competitive with Cu ones, intercalated MLGNR arrangements must be considered.

Fig. 23.18

Per-unit-length electrical resistance values predicted for GNR on-chip interconnects vs wire width (technology node). Several realizations of GNR lines are considered, differing from the edge-scattering coefficients, the Fermi level, and the mean free path , and compared to two realizations of Cu lines with two different aspect ratios, W/T. (Reprinted, with permission, from Rakheja et al. [98]. Copyright (2013) IEEE)

The available measured values for the electrical resistance or resistivity of CNT on-chip interconnects are generally far from the simulation results presented above or similar ones available in the literature [118]. The best performances obtained so far are summarized in Table 23.6, covering both vertical arrangements, such as on-chip CNT vias, and horizontal ones. As examples of the two types of interconnects, we report in Fig. 23.19 a CNT horizontal interconnect [89] and in Fig. 23.20 a CNT used to contact two transistors at different layers [119].

Table 23.6 Measured electrical resistivity for on-chip CNT interconnects

Fig. 23.19

Horizontal CNT interconnects with two types of contact: (left) end-bonded; (right) all-around. (Reprinted from Chiodarelli et al. [89]. Copyright (2013), with permission from Elsevier)

Fig. 23.20

A CNT-based via used to contact transistors at two different layers: (a) top view; (b) CNT via; (c) side view. (Reprinted from Vollebregt and Ishihara [119]. Copyright (2016), with permission from Elsevier)

Another important performance indicator among the metrics to be considered for an interconnect is the propagation delay. To evaluate such a delay, we should refer to a signaling system like that schematically depicted in Fig. 23.21, where the carbon interconnect acts as a channel between a driver and a receiver. The propagation delay is of course dependent also on the equivalent circuit parameters of the devices connected to the carbon line, for instance, the equivalent capacitance of the buffer acting as the receiver. Typical results are provided in [47], where the delay associated to a circuit as that in Fig. 23.20 is studied by considering several types of CNT and GNR interconnects, assuming the ITRS [3] values for the local, intermediate, and global levels for an integrated circuit at the technology nodes of 22 and 14 nm. Carbon nanotube interconnects are supposed to be realized by means of MWCNTs or SWCNTs, and in the latter case, different metallic fractions are considered. As for the GNR ones, different values for edge-scattering coefficient p are considered. In addition, either neutral or intercalated multilayer graphene nanoribbons are considered.

Fig. 23.21

Schematic of a simple signaling system with carbon-based interconnects

Figure 23.22 shows the computed propagation delays, normalized to that predicted when assuming the interconnection to be made by copper. At the local level, carbon interconnects (except for monolayer GNR) exhibit comparable performance with respect to copper ones, due to the huge impact of the driver resistance over the propagation delay at such a level. The MWCNT solution is sensibly better for longer lines. At the intermediate level, usually the CNT lines outperform copper ones, and this behavior is much more pronounced at the global level. As for the GNR solution, Fig. 23.22 suggests that the only way to outperform copper is to realize doped GNRs with an edge-scattering coefficient p = 1, which is an ideal case, since realistic values are about 0.4–0.5. Lower propagation delays for GNR interconnects even in cases of low values of the coefficient p are predicted in [98], where an optimal number of layers is chosen to minimize such a delay.

Fig. 23.22

Signal delay values for the signaling system in Fig. 23.20 for different types of carbon interconnects, assuming two different technology nodes and hierarchical levels: (a) 14 nm, local level; (b) 22 nm, local level; (c) 14 nm, intermediate level; (d) 22 nm, intermediate level; (e) 14 nm, global level; (f) 22 nm, global level. The results are normalized to that of copper interconnect. Different values for the edge-scattering coefficient p are considered for the GNR lines that have been supposed either to be neutral (n-GNR) or intercalated (d-GNR). Different metallic fractions F_m are considered for SWCNT lines. (Reprinted, with permission, from Li et al. [47]. Copyright (2009) IEEE)

Figure 23.23 shows the delays obtained by considering GNR interconnects with two different values of mean free path λ_D and by considering both the side and the top contact solutions. Despite the low value of p, this optimized solution improves the performance at the local level, becoming better or comparable to copper, whereas at the intermediate level, the GNR solution is still worse.

Fig. 23.23

Signal delay values for different types of GNR interconnects compared to copper one, versus the technology nodes and hierarchical levels: (a) local level, with driver size line length equal to 1× and 10× gate pitches, respectively; (b) with driver size line length equal to 5× and 50× gate pitches, respectively. Different values for the mean free λ_D are considered, and top and side contact configurations are simulated. The edge-scattering coefficient p is equal to 0.2. (Reprinted, with permission, from Rakheja et al. [98]. Copyright (2013) IEEE)

Another important issue for a signaling system is signal integrity : a popular technique to check the signal integrity of a transmitting channel for high-speed digital signals is the analysis of the so-called eye diagram that is obtained by overlapping segments of a digital data stream arriving at the receiver in the same time frame [8]. The quality of the transmitting system is given by two metrics: the eye- jitter (related to the signal delays and responsible for synchronization errors) and the eye-opening factor (related to the signal distortion and responsible for false detections). To realize a good channel, the first indicator must be kept as low as possible, while the second should be as high as possible. Although the eye diagram features depend, of course, on the whole system given by the driver, interconnect, and receiver, the effects of the interconnect become more and more crucial as the frequencies increase and the dimensions decrease [8]. In particular, both the static and dynamic parameters of the interconnect influence the performance of the digital system.

In the following, a local-level system is analyzed, where the carbon interconnect in Fig. 23.20 is assumed to be composed by a horizontal trace at metal layer M1 and another horizontal trace at metal layer M2, with a via connecting M1 to M2. The technology node considered is 22 nm, with parameters as in Table 23.1. The interconnect is assumed to be made of bundles of SWCNTs of diameter 1 nm, with a metallic fraction F_m = 0.3. The driver is modeled as a voltage source of magnitude V_s = 0.8V_DD and a series resistor of 2.5kΩ, while the receiver is modeled as a capacitor of capacitance 2 fF. Figure 23.24 shows the eye diagrams computed for such a system, with different values of data rate (DR) and rise time t_r. Table 23.7 summarizes the computed values for the jitter and the opening factor for different DR, showing the capability of the CNT solution to outperform the copper one.

Fig. 23.24

Eye diagrams for the circuit in Fig. 23.20, assuming an on-chip interconnect at the local level (22 nm technology node), at different data rate (DR) values: (a) CNT case, DR = 5Gbit/s; (b) Cu case, DR = 5Gbit/s; (c) CNT case, DR = 10Gbit/s; (d) Cu case, DR = 10Gbit/s

Table 23.7 Summary of the results of the eye diagram analysis for on-chip interconnects

23.4.2 Through-Silicon Vias and Pillar Bumps

As pointed out in Sect. 23.2, from a technology point of view, the fabrication of vertical bundles of CNTs has reached satisfactory levels in terms of density, direction control, CMOS compatibility, and contact resistance. Consequently, CNTs are proposed as serious candidates for realizing vertical interconnects like through-silicon vias and pillar bumps.

Through-silicon vias (TSVs) are vertical interconnects passing through stacked integrated circuits (ICs), a solution that has enabled the so-called 3D-IC technology providing many benefits such as reduced delay, increased bandwidth, and energy efficiency [123, 124]. Pillar bumps are vertical interconnects used in the chip-to-package and chip-on-chip bonding technology, to replace costly past solutions like wire bonding [125]. Both types of interconnects suffer from two main problems: the electromigration of copper atoms due to the high current density and the skin effect due to the high frequency. Therefore, in the past years, carbon nanotube interconnects have been proposed in order to mitigate such problems. As pointed out in Sect. 23.1, CNTs may carry a current density of about 10⁹ A/cm² [21], two orders of magnitude higher than the maximum value obtainable for Cu, so exhibiting a high electromigration resistance [126]. In addition, the high-frequency behavior of the CNT bundles is better than the Cu solution [127, 128], for instance, due to a lower sensitivity to the skin effect [129].

From a theoretical point of view, this is due to the role of the huge kinetic inductance which usually hides the magnetic one, as pointed out in Sect. 23.2.2. Specifically, if we realize a TSV (of cross section S_b and height l) with a bundle of N_b CNTs, and assume the equivalent single-conductor model described in Sect. 23.2.3, the relation between the total current in the bundle, ${I}_b={\sum}_{n=1}^{N_b}{I}_n,$and the voltage V_b can be expressed as:

$$ {V}_b={Z}_b{I}_b=\left({\uprho}_b^{\prime }+i{\uprho}_b^{{\prime\prime}}\right)\frac{l}{S_b}{I}_b, $$

(23.22)

where ${\uprho}_b={\uprho}_b^{\prime }+i{\uprho}_b^{{\prime\prime} }$ may be regarded as the bundle equivalent resistivity. Assuming that all CNTs in the bundle are equal and that the kinetic inductance dominates over the magnetic one, the equivalent resistivity becomes [47]:

$$ {\uprho}_b^{\prime }+i{\uprho}_b^{{\prime\prime} }={\uprho}_0\left(1+i\upomega /\upnu \right), $$

(23.23)

where ν is the collision frequency and the DC value ρ₀ is given by:

$$ {\uprho}_0=\frac{R_{CNT}{S}_b}{F_M{N}_bl}, $$

(23.24)

being R_CNT the resistance of the single CNT and F_M the metal fraction. As for the resistance value, similar considerations hold as those expressed for conventional on-chip vias in Sect. 23.4.1. However, TSVs or pillar bumps are characterized by diameters of the order of μm, hence larger dimensions with respect to on-chip vias analyzed in Sect. 23.4.1, and hence their electrical resistance values are usually higher than for the copper realization, since the copper resistivity value is in the bulk value region (see Fig. 23.2). Therefore, the use of CNT improves the reliability but usually worsens the electrical performance of such interconnects. A possible compromise is the use of Cu-CNT composite [130].

For high frequencies, also the imaginary part of resistivity (related to the inductance) plays a role. We can define an equivalent skin depth as follows [47]:

$$ \updelta =\sqrt{\frac{2{\uprho}_0}{\upomega \upmu}}\sqrt{\left[{\left(\frac{\upomega}{\upnu}\right)}^2+1\right]\left(\sqrt{{\left(\frac{\upomega}{\upnu}\right)}^2+1}-\frac{\upomega}{\upnu}\right)}. $$

(23.25)

Expression (23.25) reduces to the classical definition of the skin depth if ω/ν <  < 1, i.e., when the mean free path is small enough (e.g., ~40 nm in copper). For CNTs, however, larger mean free path values (hundreds of μm) induce a saturation in the skin depth as frequency increases, according to (23.25).

As an example, let us consider a TSV with the typical dimensions predicted by the ITRS [3] for the 14 nm technology, i.e., diameter equal to 1.2 μm and height equal to 30 μm, assuming a current of 10 mA flowing through it. Let us consider the TSV to be made either by copper (assuming the resistivity parameters given in Fig. 23.2 for bulk copper) or by a bundle of MWCNTs. Each MWCNT has outer diameter D_out = 30 nm and inner diameter D_in = 0.5D_out, with one-third of metallic shells. Figure 23.25 shows the distribution in the via cross section of the current density computed at room temperature at a frequency of 200 GHz. Figure 23.25a refers to the copper via, where the skin effect is evident, whereas Fig. 23.25b referring to the MWCNT case shows a quite uniform current density. To clarify the role of the kinetic term in the inductance, Fig. 23.25c shows the result obtained for the MWCNT case after removing the kinetic inductance: in this case, the skin effect is again no longer negligible.

Fig. 23.25

Distribution of the current density in the cross section of a TSV for the 14 nm technology at 200 GHz: (a) Cu; (b) MWCNT; (c) MWCNT without the effect of the kinetic inductance L_k (Reprinted, with permission, from Chiariello et al. [56]. Copyright (2103), IEEE)

The presence of the kinetic inductance also provides benefits in terms of EMC behavior of the interconnects, by mitigating, for instance, the proximity effect [36] and the crosstalk noise between adjacent interconnects [54, 131]. Indeed, new concepts and new solution for the EMC problems at the nanoscale arise due to the features of parameters like the kinetic inductance or the quantum capacitance, as shown in [10].

One of the reasons to use CNT bundles as pillar bumps (e.g., Fig. 23.3) is the possibility to achieve good reliability performance while implementing new heat removal technologies. Indeed, the heat management of future nanoelectronics requires new approaches: using the conventional approach, for instance, the cooler for technology solutions like the systems in package could easily become larger than the semiconductor itself. Carbon nanotubes could, for instance, be used as microchannel coolers in thermofluidic cooling approaches. In addition, they are also proposed as a thermal interface material , although the main limit is still given by the possibility of achieving high-density aligned CNTs in a polymer matrix, without degrading the thermal conductivity [15].

In order to investigate the electrical properties of CNT pillar bumps, let us refer to the scheme depicted in Fig. 23.7a: the two vertical pillars are assumed to be realized by using Cu, a bundle of SWCNTs, or a bundle of MWCNTs. As usual, we assume that only one-third of the total CNT shells are metallic. As pointed out in Sect. 23.2, since the semiconducting SWCNTs do not contribute to the conduction, very high-density bundles must be fabricated to have low-resistance CNT pillars. In MWCNTs, on the other hand, the semiconducting shells also contribute to the total number of conducting channels, and therefore the optimal density is a trade-off between the CNT diameter and its number of shells. Let us consider the pillar bumps proposed in [132], having a diameter D = 15 μm and a wire bond pitch of 30 μm, assuming an operating frequency of 10 GHz. For the Cu solution, we can assume the bulk value of resistivity, i.e., ρ_Cu = 1.7 ⋅ 10⁻⁸ Ωm.The SWCNT diameters are assumed to be 2 nm, whereas for the MWCNTs, we assume an outer diameter D_out = 30nm, inner diameter D_in = 0.5D_out, and an inter-shell distance 0.34 nm. In both cases, a density of 80% and a contact resistance of 20 kΩ per shell are assumed.

In terms of electrical properties, a good packaging interconnect must be characterized by a low equivalent series impedance. For this case, the equivalent inductances are well beyond the maximum allowed of 5 − 10 pH; hence we can focus on the equivalent resistance. Figure 23.26 compares the resistance values obtained for Cu and CNT bumps, for aspect ratios ranging from 1 to 5. The lowest values are obtained by using MWCNT bundles, whereas SWCNT bundles show higher resistance values, close to those related to the copper realization. Note that at the given frequency, the skin effect in the copper pillar plays a relevant role: indeed, the resistance obtained by neglecting the skin effect would be much lower, as shown in Fig. 23.26. The performance of SWCNTs can be further improved by reducing the contact resistance.

Fig. 23.26

Equivalent resistance of pillar bumps made by carbon nanotube and copper. The solution obtained by neglecting the skin effect in the copper bump is also plotted

23.4.3 Power Interconnects

As already pointed out, carbon materials are considered to be promising candidates for the realization of novel power interconnects in next-generation ICs, given the possibility to match two major requirements for building resilient power delivery networks (PDNs): higher current density and efficient heat management. Indeed, future PDNs are required to carry current densities of the order of MA/cm², corresponding to a volumetric heat production of the order of 10³–10⁴ W/mm³, which would be impossible if the PDNs were fabricated out of conventional metals, like copper and aluminum.

The electrical behavior of power interconnect in terms of resistance, frequency dependence, and current density is similar to that of on-chip interconnects previously analyzed in Sect. 23.4.1. However, speaking about power interconnects, it is of interest to provide additional results about their electrothermal behavior, starting from the considerations given in Sect. 23.2.4. Taking into account electrothermal effects is, of course, also important for on-chip interconnects or TSVs [115], but it becomes a must when dealing with power interconnects. Indeed, in PDNs the power dissipation induces elevated temperatures, which directly impact interconnect parameters (i.e., R, L, and C values), since material properties such as the electrical resistivity are temperature dependent. Ultimately, any change in interconnect parameters varies both dynamic and leakage power consumption and impacts the so-called power integrity by modifying the performance indicators such as the voltage drop (a measure of the unwanted voltage fluctuations over the PDN).

The thermal impact on PDNs may be mitigated due to the favorable thermal properties of CNTs and graphene with respect to traditional materials. Specifically, it is possible to tailor the carbon interconnect characteristics in order to have an electrical resistance quite insensitive to the temperature variation or even decreasing with increasing temperature. As already mentioned in Sect. 23.2.4, this favorable behavior is the consequence of a counteracting mechanism between the increase of the number of conducting channels M (23.21) and the decrease of the mean free path l_mfpas the temperature increases. Both parameters influence the electrical resistance of a carbon interconnect, as shown in (23.10) and (23.11).

The temperature dependence of an electrical resistance R(T) is usually studied by means of the temperature coefficient of the resistance (TCR), defined as:

$$ TCR=\frac{1}{R}\frac{dR}{dT}. $$

(23.26)

Conventional conducting materials always exhibit a TCR > 0, i.e., an electrical resistance that increases with increasing temperature. Let us consider the popular law for the temperature dependence of the resistance of a copper wire of length l and cross-section S:

$$ R(T)={\uprho}_0\left(1+{\upalpha}_0\left(T-{T}_0\right)\right)\frac{l}{S}, $$

(23.27)

where T₀ is the room temperature, ρ₀ is the resistivity at T = T₀, and α₀ is a temperature coefficient. Both ρ₀ and α₀ depend on the transverse dimension of the copper interconnect: for instance, for bulk conductors, it is ρ₀ ≈ 1.7 ⋅ 10⁻⁸ Ωm and α₀ = 0.0039 K^‐1, whereas for nanoscale ones (for instance, at the 22 nm node), it is α₀ = 0.0012 K^‐1 and ρ₀ ≈ [2 → 6] μΩcm, depending on the considered interconnect level. By applying (23.26)–(23.27), we obtain TCR = α₀, which means that for copper, this value is always positive and slightly decreasing at the nanoscale. Instead, by applying (23.26) to the resistance of a carbon interconnect (23.10)–(23.11), it is possible to obtain a much more complicated behavior of the TCR that depends on temperature itself but also on the line length, given the different roles played by the intrinsic and contact resistances. In particular, a more realistic model for the parasitic term R_p in (23.11) must take also into account the dependence on temperature T, whereas the quantum term R₀ is constant with T. A simple model for R_p is suggested in [63] and resembles (23.27), assuming as S the contact area and as l a characteristic length of the contact.

Taking into account also the latter consideration, the TCRs computed for CNT and Cu interconnects at room temperature are reported in Fig. 23.27. Here, metallic CNTs are considered, with two different diameters values: 1 and 3 nm for SWCNTs and 20 nm and 40 nm for MWCNTs. As for the parasitic resistance, here we assume R_p(T₀) = 1 kΩ and α₀ = 10⁻⁴ K⁻¹. The TCR for SWCNTs is always positive: this is due to the fact that for such CNTs, the number of channels M is quite insensitive to T; see (23.21) and Table 23.3. Instead, TCRs close to zero or even negative may be obtained by using MWCNTs: the lengths for which the TCR is negative can be modulated by changing the dimension of the diameters or by modifying the impact of the parasitic resistance.

Fig. 23.27

Temperature coefficient of the resistance versus line length, for Cu and SWCNT and MWCNT for two different sizes, at T = 300 K

Experimental evidence of a negative TCR has been provided for isolated MWCNTs [20] and GNRs [62]. However, when the CNTs are bundled, such a behavior often disappears due to the collective effects and the degradation of the contacts. Few examples of bundled CNTs with negative TCRs are available so far: in [63] this behavior has been experimentally found for MWCNT vias with lengths up to 3 μm, also putting on evidence the side effects due to contact resistance. A similar result is found in [80], again for CNT vias. Recently, a negative TCR has been obtained also in longer (hundreds of μm) horizontal conductors, realized by CNT bundles [84].

To investigate the electrothermal performance of a carbon-based power delivery network, let us consider the simple structure sketched in Fig. 23.28, where a power and ground plane are separated by an insulation layer and connected to VDD and GND supply pins, respectively. The chip is connected to a heat sink on one side for heat dissipation. The electrical model is given by two networks corresponding to the two layers. At each grid node, the conductors are represented by means of a series impedance; see Fig. 23.28b. Each node of a grid is connected to the corresponding one on the other grid via a capacitor in parallel with a current source to represent the circuit switching activity, i.e., the current demand of a circuit connected between VDD and GND pins. The solution of the electrical problem provides the so-called voltage drop at any generic node i, namely:

Fig. 23.28

The considered power delivery network: (a) schematic of the two-layer structure, with the heat sink; (b) equivalent electrical and (c) thermal circuit model at each grid node (Reprinted, with permission, from Magnani et al. [117]. Copyright (2016) IEEE)

$$ {V}_d(i)={V}_{DD}-\left({V}_n(i)-{V}_g(i)\right) $$

(23.28)

V_n(i) and V_g(i) being the node potentials with respect to the power and ground plane references, respectively.

As for the thermal problem, the temperature distribution over the PDN is found by solution of a heat equation like (23.17). However, in PDNs it is possible to assume that the heat mainly flows along the grid conductors (grids and vias), the heat exchange between copper and dielectric being negligible. Therefore, (23.17) may be discretized with an equivalent thermal circuit whose generic node is depicted in Fig. 23.28c, R_TH being the thermal resistance corresponding to the generic track of the conductor and R_HS the heat sink resistance.

In other words, the thermal problem may be cast as an equivalent electrical one, where the heat flow plays the role of the electrical current and the temperature difference corresponds to the electrical voltage.

As pointed out in Sect. 23.2.4, the coupling between the two problems is given by the production term in (23.17): this term corresponds in Fig. 23.28c to the source P_s + P_J, being the two terms related to the switching activity and to the Joule effect in the conductors, respectively. Therefore, this term depends on the solution of the electrical problem. On the other hand, the solution of the thermal problem changes the electrical resistance values, according to (23.27) or similar laws. A popular way to solve this coupled problem is through the so-called relaxation approach where, after giving an initial guess for the temperature, iteratively the heat equation is solved providing the temperature distribution, the temperature-dependent electrical parameters are updated, and the electrical problem is solved. Then, the heat production term is updated, until convergence is reached.

To study the performance of a carbon PDN, let us refer to a global-level interconnect at the 22 nm technology node (Table 23.1), with a chip core of dimensions 0.5 × 0.5 mm. The PDN grid is made of 250 × 250 nodes and is fed at the four corners of each elementary stamp of 25 × 25 nodes. The thermal resistance of the heat sink is assumed to be 100× the value of the thermal resistance of a single PDN branch. For such a case, the dynamic effects can be neglected, as shown in [117]; hence a pure resistive model can be assumed. As for the copper realization, we assume for the resistance the classical model (23.27) with the room temperature parameters typical for the 22 nm technology, namely, ρ₀ = 2.94 μΩcm and α₀ = 0.0012 K^‐1. The copper thermal conductivity is assumed to be k_m = 193 W/mK.

As for the carbon PDNs, we consider a case where the interconnects are made by bundles of MWCNTs of 40 nm external diameters, 80% density, and metallic fraction of 1/3. For MWCNTs, a thermal conductivity of 200 W/mK was assumed. Note that this value of thermal conductivity is far from the values of above 3000 W/mK, reported, for instance, in [24]. Such outstanding values, however, correspond to favorable cases with excellent control of the CNT quality, e.g., in terms of alignment. A more realistic case must take into account the effect of intra-bundle coupling, imperfections, and misalignment, which typically lower the thermal conductivity of about one order of magnitude.

Next, a graphene realization is also considered, by assuming each track of the PDN to be made by a stack of GNRs, put at the van der Waals distance, with a metallic fraction of 1/3. As for the thermal conductivity, we assume a realistic value of 1500 W/mK. For both the CNT realizations, we neglect the contribution of the parasitic term in the contact resistance in (23.11); therefore we consider ideal contacts.

In Fig. 23.29 we report the results of the performance analysis of the considered PDNs, carried out by computing the maximum voltage drop (23.28) in Fig. 23.29a and the maximum temperature rise in Fig. 23.29b, over the PDN nodes, for different values of the switching current. The CNT realization provides the best electrical and thermal performance, with a voltage drop always lower than 0.1 V and a temperature rise not exceeding 50 K. In addition, CNT power interconnects perform well in a wide range of the switching current I₀. The GNR realization is always worse than the CNT one, both in terms of voltage drop and of temperature rise. Given the above dimensions and parameters, the total number of channels for GNRs is lower than for MWCNTs, leading to higher electrical resistance values for GNR power interconnects. Compared to the copper realization, the GNR one provides a higher voltage drop for low values of I₀, but for higher values, the behavior is much better. However, in terms of thermal behavior, the GNR solution outperforms the Cu one. If we include the effect of the parasitic contact resistance, we expect to have a similar behavior, but a reduced range of admissible switching current I₀.

Fig. 23.29

Performance analysis of the PDNs, comparing Cu, CNT, and GNR cases: (a) maximum voltage drop, (b) maximum temperature rise, vs current source

23.5 Conclusions

As the electronics of the twenty-first century is approaching the end of the classical roadmap, carbon materials are serious candidates to replace conventional ones in realizing novel interconnects. The main reason for such an interest lies in the outstanding electrical, thermal, and mechanical properties of carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), suggesting that carbon-based interconnects may meet the tight requirements for the future ultra-scaled technology, in terms of current density , power consumption, signal and power integrity, heat management, mechanical stresses, reliability, and resiliency.

Given this interest, in the past decade, an intense modeling activity has provided simple although more and more accurate equivalent circuit models to describe interconnects made by CNTs or GNRs. The most common modeling approach is based on a compromise between the need for models simple enough to be integrated in the standard design flow of the IC designers and the need for an accurate inclusion of the quantum effects arising at the nanoscale. This goal has been achieved by modeling the carbon interconnects in the frame of the transmission line model, where the classical magnetic and electrical parameters are corrected by novel terms taking into account kinetic and quantum effects at nanoscale. These terms are responsible for novel behavior and phenomena that give to such interconnects many favorable properties but also set some serious limits to their practical use.

Electrical and thermal ballistic transport, reduced delay, insensitivity to skin effect, mitigation of electromigration, and thermal stability are among the fascinating properties foreseen by the simulation results. On the other hand, huge resistance due to the contacts and slow propagation velocity are some of the main expected drawbacks. Simulation results for carbon-based signal and power on-chip interconnects, through-silicon vias and pillar bumps, confirm the possibility for such interconnects to outperform the classical copper ones for scaled technologies, with typical dimensions equal to or less than tens of nanometers.

In practical applications, the promising results coming from simulations are strictly related to the possibility of realizing high-quality bundles of CNTs or stacks of GNRs, with a satisfactory control over parameters like chirality, density, alignment, defects, surface roughness, and contacts. Therefore, major efforts have been made in the last years to assess reliable design approaches and effective fabrication processes for carbon interconnects. Although technological solutions have been demonstrated to solve issues like the compatibility of the growth temperature with the standard CMOS technology, the needed density and degree of alignment, the presence of defects, and the contact quality, these solutions are still not suitable for mass production, which would require a monolithic integration of carbon interconnects into future VLSI circuits. Therefore, only limited performances have been achieved with carbon interconnects so far, and few examples of integration with CMOS technology have been demonstrated. In other words, up to now carbon materials have failed to deliver their promise of realizing better interconnects with respect to conventional materials. The most promising progress could be witnessed in the development of hybrid copper/carbon materials or in the smart use of dopants and functionalization. Novel perspectives can also be given by the rapid development of stackable technology, where the interconnects are requested to link many layers of active components. Carbon electronics using 2D materials like graphene in the active x-y layers with vertical (z-axis) CNT interconnects, at least for local connections, may be the best solution to realize an all-carbon interconnection structure.