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Nanopackaging: Nanotechnologies and Electronics Packaging

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Nanopackaging

Abstract

Level one electronics packaging is traditionally defined as the design and production of the encapsulating structure that provides mechanical support, environmental protection, electrical signal and power I/O, and a means of heat dissipation for the Si chip, whether digital or analog, processor, or memory. Level two packaging is then the integration of these packaged chips into a board-level system that similarly provides mechanical support, power and signal delivery and interconnections, and thermal dissipation. Of course, nowadays the chip is often mounted directly on the board (chip-on-board, direct chip attach, flip chip), and the packaging process actually begins with the chip fabrication (wafer-level packaging), e.g., with solder bumping. The underlying principles of the field are covered in textbooks [1–3], and a multitude of others, e.g. [4], are more research focused. The field is inherently multidisciplinary with electrical, mechanical, and thermal design at its core, with all of these subject to reliability studies and material selection. Figure 1.1 shows the history of the electronics package from the vacuum tube to a multi-chip “system in a package” (SiP). The package has always been the limiting factor to system performance, i.e., the Si chip can operate at higher frequencies than the package.

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    James E. Morris

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Morris, J.E. (2018). Nanopackaging: Nanotechnologies and Electronics Packaging. In: Morris, J. (eds) Nanopackaging. Springer, Cham. https://doi.org/10.1007/978-3-319-90362-0_1

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