Abstract
Modern FPGAs consist of millions of logic resources allowing hardware designers to map increasingly large designs. However, the design productivity of mapping large designs is greatly affected by the long runtime of FPGA CAD flow. To mitigate it, modular design methodology has been introduced in the past that allows designers to partition large designs into smaller modules and compile & test the modules individually before assembling them together to complete the compilation process. Automated decision making on placing these modules on FPGA, however, is a slow and tedious process that requires large database of pre-compiled modules, which are compiled on a large number of placement positions. To accelerate this placement process during modular designing, in this paper we propose an ANN based performance estimation technique that can rapidly suggest the best shape and location for a given module. Experimental results on legacy as well as state-of-the-art FPGA devices show that the proposed technique can accurately estimate the \(F_{max}\) of modules with an average error of less than 4%.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Altera. https://www.altera.com/
CycloneII FPGAs. https://www.altera.com/products/fpga/cyclone-series/cyclone-ii/support.html
Increasing Productivity with Quartus II Incremental Compilation. https://goo.gl/uy225f
Neural Network Toolbox. https://www.mathworks.com/products/neural-network.html
PlanAhead Design and Analysis Tool. https://www.xilinx.com/products/design-tools/planahead.html
Vivado Design Suite User Guide-Hierarchical Design. https://goo.gl/6bUqqD
Xilinx. https://www.xilinx.com/
Coole, J., et al.: BPR: fast FPGA placement and routing using macroblocks. In: CODES+ISSS (2012)
Frangieh, T., et al.: A design assembly framework for FPGA back-end acceleration. Microprocess. Microsyst. 38, 889–898 (2014)
Gort, M., et al.: Design re-use for compile time reduction in FPGA high-level synthesis flows. In: FPT (2014)
Gupta, S., et al.: CAD techniques for power optimization in Virtex-5 FPGAs. In: Custom Integrated Circuits Conference, CICC 2007. IEEE (2007)
Haroldsen, T., et al.: Rapid FPGA design prototyping through preservation of system logic: a case study. In: FPL (2013)
Herath, K., et al.: Communication-aware partitioning for energy optimization of large FPGA designs. In: GLSVLSI (2017)
Lavin, C., et al.: HMFlow: accelerating FPGA compilation with hard macros for rapid prototyping. In: FCCM (2011)
Lavin, C., et al.: Impact of hard macro size on FPGA clock rate and place/route time. In: FPL (2013)
Lee, K., et al.: Shape exploration for modules in rapid assembly workflows. In: ReConFig (2015)
Love, A., et al.: In pursuit of instant gratification for FPGA design. In: FPL (2013)
Ludwin, A., et al.: Efficient and deterministic parallel placement for FPGAs. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 16, 1–23 (2011)
Mao, F., et al.: Dynamic module partitioning for library based placement on heterogeneous FPGAs. In: RTCSA (2017)
Murray, K.E., et al.: Titan: enabling large and complex benchmarks in academic CAD. In: 2013 23rd International Conference on Field Programmable Logic and Applications (FPL) (2013)
Pouchet, L.N.: Polybench: the polyhedral benchmark suite (2012). http://web.cs.ucla.edu/~pouchet/software/polybench/ (2012)
Rabozzi, M., et al.: Floorplanning for partially-reconfigurable FPGA systems via mixed-integer linear programming. In: FCCM (2014)
Tessier, R.: Fast placement approaches for FPGAs. TODAES 7, 284–305 (2002)
Trimberger, S.M.: Three ages of FPGAs: a retrospective on the first thirty years of FPGA technology. Proc. IEEE. 103, 3108–331 (2015)
Vipin, K., Fahmy, S.A.: Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration. In: Choy, O.C.S., Cheung, R.C.C., Athanas, P., Sano, K. (eds.) ARC 2012. LNCS, vol. 7199, pp. 13–25. Springer, Heidelberg (2012). https://doi.org/10.1007/978-3-642-28365-9_2
Wirthlin, M., et al.: Future field programmable gate array (FPGA) design methodologies and tool flows. Technical report (2008)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG, part of Springer Nature
About this paper
Cite this paper
Herath, K., Prakash, A., Srikanthan, T. (2018). Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_9
Download citation
DOI: https://doi.org/10.1007/978-3-319-78890-6_9
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-78889-0
Online ISBN: 978-3-319-78890-6
eBook Packages: Computer ScienceComputer Science (R0)