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Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling

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Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC 2018)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 10824))

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Abstract

Coarse Grained Reconfigurable Arrays have become an established approach to provide high computational performance in various environments. Several researchers have found that the achievable performance highly depends on the interface between memory and CGRA. In this contribution we show that a smart prefetching mechanism can increase the performance of the CGRA. At the same time it consumes less hardware resources and energy as state of the art prefetching mechanisms.

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Notes

  1. 1.

    Values are based on our FPGA implementation of the System (work in progress).

  2. 2.

    Also called synthesis in previous publications.

  3. 3.

    Simply setting \(f=p=0\) and increasing u will result in a worse performance because high u decrease performance as shown in [9].

  4. 4.

    Note that the number of contexts does not directly correlate to the runtime, because some contexts are executed more often as they are part of inner loops or even different kernels.

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Author information

Authors and Affiliations

  1. Department of Electrical Engineering and Information Technology, Computer Systems Group, TU Darmstadt, Darmstadt, Germany

    Lukas Johannes Jung & Christian Hochberger

Authors
  1. Lukas Johannes Jung
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  2. Christian Hochberger
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Corresponding author

Correspondence to Lukas Johannes Jung .

Editor information

Editors and Affiliations

  1. Technological Educational Institute of Western Greece, Antirrio, Greece

    Nikolaos Voros

  2. Ruhr-Universität Bochum, Bochum, Germany

    Michael Huebner

  3. Technological Educational Institute of Western Greece, Antirrio, Greece

    Georgios Keramidas

  4. Technische Universität Dresden, Dresden, Germany

    Diana Goehringer

  5. Technological Educational Institute of Western Greece, Antirio, Greece

    Christos Antonopoulos

  6. INESC-ID, Lisbon, Portugal

    Pedro C. Diniz

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Jung, L.J., Hochberger, C. (2018). Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_8

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  • DOI: https://doi.org/10.1007/978-3-319-78890-6_8

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-78889-0

  • Online ISBN: 978-3-319-78890-6

  • eBook Packages: Computer ScienceComputer Science (R0)

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