Abstract
Canonic signed digit (CSD) representation is a popular choice for realization of high speed, area efficient VLSI architectures in digital signal processing (DSP). In this paper, we address efficient FPGA based architectures for high speed two’s complement to CSD recoding using serial and look-ahead based circuitry. We have also demonstrated the feasibility of a scan based design approach integrated into the original design to facilitate fault localization. The generation of the circuit descriptions have been automated making it an attractive option for commercial viability of such a design approach.
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References
Parhi, K.K.: VLSI Digital Signal Processing Systems: Design and Implementation. Wiley India Pvt. Limited, Delhi (2007)
Faust, M., Gustafsson, O., Chang, C.-H.: Fast and VLSI efficient binary-to-CSD encoder using bypass signal. Electron. Lett. 47(1), 18–20 (2011)
Ruiz, G.A., Granda, M.: Efficient canonic signed digit recoding. Microelectron. J. 42(9), 1090–1097 (2011)
Herrfeld, A., Hentschke, S.: Look-ahead circuit for CSD-code carry determination. Electron. Lett. 31(6), 434–435 (1995)
Koç, Ç.K.: Parallel canonical recoding. Electron. Lett. 32(22), 2063–2065 (1996)
He, Y., Ma, B., Li, J., Zhen, S., Luo, P., Li, Q.: A fast and energy efficient binary-to-pseudo CSD converter. In: 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 838–841 (2015)
Tanaka, Y.: Efficient signed-digit-to-canonical-signed-digit recoding circuits. Microelectron. J. 57, 21–25 (2016)
Modi, H., Athanas, P.: In-system testing of Xilinx 7-series FPGAs: part 1-logic. In: IEEE International Conference for Military Communications (MILCOM), pp. 477–482 (2015)
Naouss, M., Marc, F.: Modelling delay degradation due to NBTI in FPGA look-up tables. In: 26th International Conference on Field Programmable Logic and Applications (FPL), pp. 1–4 (2016)
Naouss, M., Marc, F.: FPGA LUT delay degradation due to HCI: experiment and simulation result. Microelectron. Reliab. 64(C), 31–35 (2016)
Gupte, A., Vyas, S., Jones, P.H.: A fault-aware toolchain approach for FPGA fault tolerance. ACM Trans. Design Autom. Electron. Syst. 20(2), 32:1–32:22 (2015)
Kyriakoulakos, K., Pnevmatikatos, D.: A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support. In: 19th International Conference on Field Programmable Logic and Applications (FPL), pp. 193–198 (2009)
Nazar, G.L., Carro, L.: Fast error detection through efficient use of hardwired resources in FPGAs. In: 17th IEEE European Test Symposium (ETS), pp. 1–6 (2012)
Palchaudhuri, A., Dhar, A.S.: Efficient implementation of scan register insertion on integer arithmetic cores for FPGAs. In: 29th International Conference on VLSI Design, pp. 433–438 (2016)
Basha, B.C., Pillement, S., Piestrak, S.J.: Fault-aware configurable logic block for reliable reconfigurable FPGAs, In: IEEE International Symposium on Circuits and Systems (ISCAS). pp. 2732–2735 (2015)
Wheeler, T., Graham, P., Nelson, B., Hutchings, B.: Using design-level scan to improve FPGA design observability and controllability for functional verification. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 483–492. Springer, Heidelberg (2001). https://doi.org/10.1007/3-540-44687-7_50
Ehliar, A.: Optimizing Xilinx designs through primitive instantiation. In: Proceedings of the 7th FPGAworld Conference, FPGAworld 2010, pp. 20–27. ACM, New York (2010)
Palchaudhuri, A., Chakraborty, R.S.: High Performance Integer Arithmetic Circuit Design on FPGA: Architecture Implementation and Design Automation. Springer India, New Delhi (2016). https://doi.org/10.1007/978-81-322-2520-1
Xilinx Inc.: 7 Series FPGAs Configurable Logic Block User Guide UG474 (v1.8) 27 Sep 2016. https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
Hwang, K.: Computer Arithmetic: Principles Architecture and Design. Wiley, Hoboken (1979)
Zicari, P., Perri, S.: A fast carry chain adder for Virtex-5 FPGAs. In: 15th IEEE Mediterranean Electrotechnical Conference (MELECON), pp. 304–308 (2010)
Källström, P., Gustafsson, O.: Fast and area efficient adder for wide data in recent Xilinx FPGAs. In: 26th International Conference on Field Programmable Logic and Applications (FPL), pp. 1–4 (2016)
Wheeler, T.B.: Improving design observability and controllability for functional verification of FPGA-based circuits using design-level scan techniques. Master’s thesis. Brigham Young University (2001)
Wheeler, T., Graham, P., Nelson, B., Hutchings, B.: Using design-level scan to improve FPGA design observability and controllability for functional verification. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 483–492. Springer, Heidelberg (2001). https://doi.org/10.1007/3-540-44687-7_50
Toutounchi, S., Lai, A.: FPGA test and coverage. In: International Test Conference, pp. 599–607 (2002)
Palchaudhuri, A., Amresh, A.A., Dhar, A.S.: Efficient automated implementation of testable cellular automata based pseudorandom generator circuits on FPGAs. J. Cell. Autom. 12(3–4), 217–247 (2017)
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Palchaudhuri, A., Dhar, A.S. (2018). Fast Carry Chain Based Architectures for Two’s Complement to CSD Recoding on FPGAs. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_43
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