Abstract
This paper presents an orderly dataflow-optimisation approach suitable for area-energy aware computer vision applications on FPGAs. Vision systems are increasingly being deployed in power constrained scenarios, where the dataflow model of computation has become popular for describing complex algorithms. Dataflow model allows processing datapaths comprised of several independent and well defined computations. However, compilers are often unsuccessful in identifying domain-specific optimisation opportunities resulting in wasted resources and power consumption. We present a methodology for the optimisation of dataflow networks, according to patterns often found in computer vision systems, focusing on identifying optimisations which are not discovered automatically by an optimising compiler. Code transformation using profiling and refactoring provides opportunities to optimise the design, targeting FPGA implementations and focusing on area and power abatement. Our refactoring methodology, applying transformations to a complex algorithm for visual tracking resulted in significant reduction in power consumption and resource usage.
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Brunei, S.C., Mattavelli, M., Janneck, J.W.: Turnus: a design exploration framework for dataflow system design. In: International Symposium on Circuits and Systems (ISCAS), p. 654 (2013)
Brunet, S.C., Mattavelli, M., Janneck, J.W.: Buffer optimization based on critical path analysis of a dataflow program design. In: International Symposium on Circuits and Systems (ISCAS), pp. 1384–1387 (2013)
Comaniciu, D., Ramesh, V., Meer, P.: Kernel-based object tracking. IEEE Trans. Pattern Anal. Mach. Intell. 25(5), 564–577 (2003)
Ge, R., Vogt, R., Majumder, J., Alam, A., Burtscher, M., Zong, Z.: Effects of dynamic voltage and frequency scaling on a k20 GPU. In: 42nd International Conference on Parallel Processing, pp. 826–833 (2013)
Hueske, F., Peters, M., Krettek, A., Ringwald, M., Tzoumas, K., Markl, V., Freytag, J.C.: Peeking into the optimization of data flow programs with MapReduce-style UDFs. In: International Conference on Data Engineering (ICDE), pp. 1292–1295 (2013)
Janneck, J.W., Miller, I.D., Parlour, D.B., Roquier, G., Wipliez, M., Raulet, M.: Synthesizing hardware from dataflow programs: an MPEG-4 simple profile decoder case study. In: IEEE Workshop on Signal Processing Systems (SiPS), pp. 287–292 (2008)
Kim, Y., Jadhav, S., Gloster, C.S.: Dataflow to hardware synthesis framework on FPGAs. In: International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW), pp. 91–96 (2016)
Lee, E.A., Parks, T.M.: Dataflow process networks. Proc. IEEE 83(5), 773–801 (1995)
Malik, M., Farahmand, F., Otto, P., Akhlaghi, N., Mohsenin, T., Sikdar, S., Homayoun, H.: Architecture exploration for energy-efficient embedded vision applications: from general purpose processor to domain specific accelerator. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 559–564 (2016)
Pandey, B., Yadav, J., Pattanaik, M., Rajoria, N.: Clock gating based energy efficient ALU design and implementation on FPGA. In: International Conference on Energy Efficient Technologies for Sustainability (ICEETS), pp. 93–97 (2013)
Rheinländer, A., Leser, U., Graefe, G.: Optimization of complex dataflows with user-defined functions. ACM Comput. Surv. 50(3), 38:1–38:39 (2017)
Schulte, E., Dorn, J., Harding, S., Forrest, S., Weimer, W.: Post-compiler software optimization for reducing energy. SIGARCH Comput. Archit. News 42(1), 639–652 (2014)
Seinstra, F.J., Koelma, D.: The lazy programmer’s approach to building a parallel image processing library. In: Proceedings 15th International Parallel and Distributed Processing Symposium (IPDPS), pp. 1169–1176 (2001)
Sérot, J., Berry, F., Bourrasset, C.: High-level dataflow programming for real-time image processing on smart cameras. J. Real-Time Image Process. 12(4), 635–647 (2016)
Stewart, R., Bhowmik, D., Wallace, A., Michaelson, G.: Profile guided dataflow transformation for FPGAs and CPUs. J. Sig. Process. Syst. 87(1), 3–20 (2017)
Stewart, R., Michaelson, G., Bhowmik, D., Garcia, P., Wallace, A.: A dataflow IR for memory efficient RIPL compilation to FPGAs. In: International Conference on Algorithms and Architectures for Parallel Processing, pp. 174–188 (2016)
Teifel, J., Manohar, R.: An asynchronous dataflow FPGA architecture. IEEE Trans. Comput. 53(11), 1376–1392 (2004)
Turcza, P., Duplaga, M.: Hardware-efficient low-power image processing system for wireless capsule endoscopy. IEEE J. Biomed. Health inform. 17(6), 1046–1056 (2013)
Yviquel, H., Lorence, A., Jerbi, K., Cocherel, G., Sanchez, A., Raulet, M.: Orcc: Multimedia development made easy. In: Proceedings of the 21st ACM International Conference on Multimedia, pp. 863–866 (2013)
Acknowledgement
We acknowledge the support of the Engineering and Physical Research Council, grant references EP/K009931/1 (Programmable embedded platforms for remote and compute intensive image processing applications), EP/K014277/1 (MOD University Defence Research Collaboration in Signal Processing).
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Garcia, P., Bhowmik, D., Wallace, A., Stewart, R., Michaelson, G. (2018). Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_42
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