Abstract
Mapping complex embedded applications to FPGA based SoCs often results in systems consisting of multiple processors to maintain high processing rates. Such systems can be created individually for each application, since FPGAs have very small non-recurring expenses. Thus, the system architecture (including the number of cores and the partitioning and distribution of tasks) must be derived and executed by the developer multiple times. In most cases it is not possible to analytically compute the design performance, so design space exploration comes into play. In this contribution we present a technique leveraging a combination of tools to (1) greatly reduce the effort to create different solutions in the design space and (2) reduce the time required for this design implementation by a factor of three. Compared to similar approaches, we claim to have a highly accurate design point evaluation and loosen the restrictions of the legacy application.
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Heid, K., Wenzel, J., Hochberger, C. (2018). Fast DSE for Automated Parallelization of Embedded Legacy Applications. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_38
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