Abstract
The well-known Triple Modular Redundancy (TMR), when applied to processors to mitigate the occurrence of faults, implies that all applications have the same level of criticality (since they are all equally protected) and are executed in a homogeneous environment, which naturally would waste precious resources in terms of area and energy. However, many current systems are composed of heterogeneous cores that implement the same ISA (e.g., ARM’s big.LITTLE or DynamIQ), executing some applications that may be more critical than others and that would require different levels of protection. With that in mind, we propose ISA-DTMR, a non-intrusive approach that, taking advantage of heterogeneous systems, can protect applications at different levels in a totally transparent fashion. By using heterogeneous multicore configurations composed of configurable processors that implement the same Instruction Set Architecture (ISA), we will show that it is possible to adapt the level of protection for each application according to its reliability requirements. When compared to homogeneous processors, ISA-DTMR reduces area by up to 54.9%, and energy consumption by 30.35%, with negligible overhead on performance, for a configuration that balances performance and energy consumption. ISA-DTMR is able to provide the same level of protection for critical applications and even improve the reliability for non-critical applications.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Arm Limited: Arm DynamIQ technology framework to design and build Cortex-A CPU systems (2017). https://developer.arm.com/technologies/dynamiq
Ashraf, R.A., Mouri, O., Jadaa, R., Demara, R.F.: Design-for-diversity for improved fault-tolerance of TMR systems on FPGAs. In: 2011 International Conference on Reconfigurable Computing and FPGAs, pp. 99–104, November 2011
Avizienis, A., Kelly, J.P.J.: Fault tolerance by design diversity: concepts and experiments. Computer 17(8), 67–80 (1984)
Beck, A.C.S., Lisbôa, C.A.L., Carro, L.: Adaptable Embedded Systems. Springer Science & Business Media, Heidelberg (2012). https://doi.org/10.1007/978-1-4614-1746-0
Bolchini, C.: A software methodology for detecting hardware faults in VLIW data paths. IEEE Trans. Reliab. 52(4), 458–468 (2003)
Bolchini, C., Carminati, M., Miele, A.: Self-adaptive fault tolerance in multi-/many-core systems. J. Electron. Test. 29(2), 159–175 (2013)
Geuskens, B., Rose, K.: Modeling Microprocessor Performance. Springer Science & Business Media, Heidelberg (2012). https://doi.org/10.1007/978-1-4615-5561-2
Kriebel, F., Rehman, S., Sun, D., Shafique, M., Henkel, J.: ASER: adaptive soft error resilience for reliability-heterogeneous processors in the dark silicon era. In: ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–6, June 2014
Kriebel, F., Shafique, M., Rehman, S., Henkel, J., Garg, S.: Variability and reliability awareness in the age of dark silicon. IEEE Des. Test 33(2), 59–67 (2016)
Littlewood, B.: The impact of diversity upon common mode failures. Reliab. Eng. Syst. Saf. 51(1), 101–113 (1996)
Mukherjee, S.S., Kontz, M., Reinhardt, S.K.: Detailed design and evaluation of redundant multi-threading alternatives. In: Proceedings 29th Annual International Symposium on Computer Architecture, pp. 99–110 (2002)
Pillai, A., Zhang, W., Kagaris, D.: Detecting VLIW hard errors cost-effectively through a software-based approach. In: 21st International Conference on Advanced Information Networking and Applications Workshops, AINAW 2007, vol. 1, pp. 811–815, May 2007
Ray, J., Hoe, J.C., Falsafi, B.: Dual use of superscalar datapath for transient-fault detection and recovery. In: MICRO-34 Proceedings of the 34th ACM/IEEE International Symposium on Microarchitecture, pp. 214–224, December 2001
Reinhardt, S.K., Mukherjee, S.S.: Transient fault detection via simultaneous multithreading. In: Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No. RS00201), pp. 25–36, June 2000
Reis, G.A., Chang, J., Vachharajani, N., Mukherjee, S.S., Rangan, R., August, D.I.: Design and evaluation of hybrid fault-detection systems. In: 32nd International Symposium on Computer Architecture (ISCA 2005), pp. 148–159, June 2005
Sabena, D., Reorda, M.S., Sterpone, L.: On the development of software-based self-test methods for VLIW processors. In: IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 25–30, October 2012
Sartor, A.L., Becker, P.H.E., Beck, A.C.S.: Simbah-FI: simulation-based hybrid fault injector. In: 2017 VII Brazilian Symposium on Computing Systems Engineering (SBESC), pp. 94–101, November 2017
Sartor, A.L., Becker, P.H.E., Hoozemans, J., Wong, S., Beck, A.C.S.: Dynamic trade-off among fault tolerance, energy consumption, and performance on a multiple-issue VLIW processor. IEEE Trans. Multi-scale Comput. Syst. 55(99), 1 (2017)
Sartor, A.L., Lorenzon, A.F., Carro, L., Kastensmidt, F., Wong, S., Beck, A.C.S.: A novel phase-based low overhead fault tolerance approach for VLIW processors. In: Computer Society Annual Symposium on VLSI, pp. 485–490, July 2015
Sartor, A.L., Wong, S., Beck, A.C.S.: Adaptive ILP control to increase fault tolerance for VLIW processors. In: Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 9–16, July 2016
Sartor, A.L., Lorenzon, A.F., Carro, L., Kastensmidt, F., Wong, S., Beck, A.C.S.: Exploiting idle hardware to provide low overhead fault tolerance for VLIW processors. J. Emerg. Technol. Comput. Syst. 13(2), 13:1–13:21 (2017)
Scott, J., et al.: Designing the low-power m* core architecture. In: IEEE Power Driven Microarchitecture Workshop. Citeseer (1998)
Shye, A., Moseley, T., Reddi, V.J., Blomstedt, J., Connors, D.A.: Using process-level redundancy to exploit multiple cores for transient fault tolerance. In: IEEE/IFIP Conference on Dependable Systems and Networks, pp. 297–306, June 2007
Sterpone, L., Sabena, D., Campagna, S., Reorda, M.S.: Fault injection analysis of transient faults in clustered VLIW processors. In: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 207–212, April 2011
Tambara, L.A., Kastensmidt, F.L., Azambuja, J.R., Chielle, E., Almeida, F., Nazar, G., Rech, P., Frost, C., Lubaszewski, M.S.: Evaluating the effectiveness of a diversity TMR scheme under neutrons. In: European Conference on Radiation and its Effects on Components and Systems (RADECS), pp. 1–5, September 2013
Wang, Z., Yang, L., Chattopadhyay, A.: Architectural reliability estimation using design diversity. In: Symposium on Quality Electronic Design, pp. 112–117, March 2015
Wong, S., van As, T., Brown, G.: \(\rho \)-VEX: A reconfigurable and extensible softcore VLIW processor. In: Conference on Field-Programmable Technology, pp. 369–372, December 2008
Acknowledgement
This work was supported in part by CNPq, FAPERGS, and CAPES.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG, part of Springer Nature
About this paper
Cite this paper
Erichsen, A.G., Sartor, A.L., Souza, J.D., Pereira, M.M., Wong, S., Beck, A.C.S. (2018). ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_19
Download citation
DOI: https://doi.org/10.1007/978-3-319-78890-6_19
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-78889-0
Online ISBN: 978-3-319-78890-6
eBook Packages: Computer ScienceComputer Science (R0)