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Low Jitter Clock Generators

  • Jeffrey Prinzie
  • Michiel Steyaert
  • Paul Leroux
Chapter
  • 641 Downloads
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

This chapter will discuss design and implementation issues for low noise clock generators in nuclear applications. This clock generator is associated with high resolution Time-to-Digital Converters. TDCs are required in several of today’s high-energy physics experiments such as CMS and ATLAS at CERN. In such applications, it is important to measure the time difference between different hit channels (originating from the detector circuits) of the experiment with single-shot precision rather than oversampling converters. The TDCs, required in those applications, are typically multichannel circuits with channel counts ranging up to 64. The TDCs are based on a timing generator which is a DLL locked to a high frequency reference clock. In this SoC, the frequency of the DLL is targeted to run at 2.56 GHz. Since the timing resolution of the TDCs is aimed in the picosecond range (3 ps bin size), the reference clock stability of the DLL becomes critical in terms of jitter or phase noise. Ideally the DLL would receive a very clean high speed clock with no uncertainty on the clock edges but in reality there will be jitter. Since this TDC will be used in LHC experiments, the circuit will use the 40 MHz reference of the accelerator which is multiplied by 64 in the PLL.

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Jeffrey Prinzie
    • 1
  • Michiel Steyaert
    • 2
  • Paul Leroux
    • 1
  1. 1.KU LeuvenGeelBelgium
  2. 2.KU LeuvenHeverleeBelgium

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