Single Shot Time-to-Digital Converters

  • Jeffrey Prinzie
  • Michiel Steyaert
  • Paul Leroux
Part of the Analog Circuits and Signal Processing book series (ACSP)


This chapter discusses the system level design and physical implementation of a single-shot TDC. In Chap.  2, various topologies were discussed to implement a Time-to-Digital converter, each of them having its own advantages and disadvantages. Since the application scope of this work is high-energy physics and space, the most important constraints are radiation tolerance, environmental effects, production yield, and of course performance.


  1. 68.
    S. Henzler, S. Koeppe, W. Kamp, H. Mulatz, and D. Schmitt-Landsiedel. 90nm 4.7ps-resolution 0.7-LSB single-shot precision and 19pj-per-shot local passive interpolation time-to-digital converter with on-chip characterization. In 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, pages 548–635, Feb 2008.Google Scholar
  2. 116.
    K Klein. The Phase-2 Upgrade of the CMS Tracker. Technical Report CERN-LHCC-2017-009. CMS-TDR-014, CERN, Geneva, Jun 2017.Google Scholar
  3. 117.
    D De Gruttola. Particle identification with the ALICE time-of-flight detector at the LHC. Journal of Instrumentation, 9(10):C10019, 2014.CrossRefGoogle Scholar
  4. 118.
    Aida Todri, M Turqueti, Ryan Rivera, and Simon Kwan. Power distribution studies for CMS forward tracker. In IEEE Nuclear Science Symposium Conference Record, pages 1208–1211, 12 2009.Google Scholar
  5. 119.
    O. Popescu. Power budgets for cubesat radios to support ground communications and inter-satellite links. IEEE Access, 5:12618–12625, 2017.CrossRefGoogle Scholar
  6. 120.
    J. R. Jenness. Radiative cooling of satellite-borne electronic components. Proceedings of the IRE, 48(4):641–643, April 1960.CrossRefGoogle Scholar
  7. 121.
    L. Perktold and J. Christiansen. A fine time-resolution 3 ps-rms time-to-digital converter for highly integrated designs. In 2013 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), pages 1092–1097, May 2013.Google Scholar
  8. 122.
    C. Ljuslin, J. Christiansen, A. Marchioro, and O. Klingsheim. An integrated 16-channel CMOS time to digital converter. IEEE Transactions on Nuclear Science, 41(4):1104–1108, Aug 1994.CrossRefGoogle Scholar
  9. 123.
    M. J. E. Lee, W. J. Dally, T. Greer, Hiok-Tiaq Ng, R. Farjad-Rad, J. Poulton, and R. Senthinathan. Jitter transfer characteristics of delay-locked loops - theories and design techniques. IEEE Journal of Solid-State Circuits, 38(4):614–621, Apr 2003.CrossRefGoogle Scholar
  10. 124.
    G. Marucci, S. Levantino, P. Maffezzoni, and C. Samori. Analysis and design of low-jitter digital bang-bang phase-locked loops. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(1):26–36, Jan 2014.CrossRefGoogle Scholar
  11. 125.
    R. Nonis, W. Grollitsch, T. Santa, D. Cherniak, and N. D. Dalt. A 2.4psrms-jitter digital PLL with multi-output bang-bang phase detector and phase-interpolator-based fractional-n divider. In 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pages 356–357, Feb 2013.Google Scholar
  12. 126.
    Y. H. Moon, I. S. Kong, Y. S. Ryu, and J. K. Kang. A 2.2-mw 135-MHz false-lock-free dll for display interface in 0.15- μm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs, 61(8):554–558, Aug 2014.Google Scholar
  13. 127.
    J. Verbeeck, M. Van Uffelen, M. S. J. Steyaert, and P. Leroux. Design of a MGy tolerant instrumentation amplifier using a correlated double sampling technique in 130 nm CMOS. In 2011 12th European Conference on Radiation and Its Effects on Components and Systems, pages 156–159, Sept 2011.Google Scholar
  14. 128.
    Masaya Miyahara, Yusuke Asada, Daehwa Paik, and Akira Matsuzawa. A low-noise self-calibrating dynamic comparator for high-speed ADCs. In 2008 IEEE Asian Solid-State Circuits Conference, pages 269–272, Nov 2008.Google Scholar
  15. 129.
    M. Lee and A. A. Abidi. A 9 b, 1.25 ps resolution coarse fine time-to-digital converter in 90 nm CMOS that amplifies a time residue. IEEE Journal of Solid-State Circuits, 43(4):769–777, April 2008.CrossRefGoogle Scholar
  16. 130.
    R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara. 1.3 v 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(3):220–224, March 2006.CrossRefGoogle Scholar
  17. 131.
    J. S. Kim, Y. H. Seo, Y. Suh, H. J. Park, and J. Y. Sim. A 300-ms/s, 1.76-ps-resolution, 10-b asynchronous pipelined time-to-digital converter with on-chip digital background calibration in 0.13- um CMOS. IEEE Journal of Solid-State Circuits, 48(2):516–526, Feb 2013.CrossRefGoogle Scholar
  18. 132.
    J. Prinzie, M. Steyaert, and P. Leroux. A self-calibrated bang bang phase detector for low-offset time signal processing. IEEE Transactions on Circuits and Systems II: Express Briefs, 63(5):453–457, May 2016.CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Jeffrey Prinzie
    • 1
  • Michiel Steyaert
    • 2
  • Paul Leroux
    • 1
  1. 1.KU LeuvenGeelBelgium
  2. 2.KU LeuvenHeverleeBelgium

Personalised recommendations