Introduction

Chapter
Part of the Computer Communications and Networks book series (CCN)

Abstract

This chapter contains some introductory information. At first, some of the arguments about the need for high computational power, parallelism, and multiprocessor systems will be presented in Sect. 1.1. The important role of interconnection networks in multiprocessor systems and parallelism will be explained in Sect. 1.2. Blocking problem will be discussed in Sect. 1.3. Crossbar network and its scalability problem will be discussed in Sect. 1.4. Finally, Sect. 1.5 will be devoted to introducing possible solutions to address the scalability and blocking problems.

References

  1. 1.
    Duato J, Yalamanchili S, Ni LM (2003) Interconnection networks: an engineering approach. Morgan Kaufmann, USAGoogle Scholar
  2. 2.
    Hennessy JL, Patterson DA (2012) Computer architecture: a quantitative approach. Elsevier, USAMATHGoogle Scholar
  3. 3.
    Grammatikakis MD, Hsu DF, Kraetzl M (2000) Parallel system interconnections and communications. CRC Press, Boca Raton, FloridaGoogle Scholar
  4. 4.
    Shiva SG (2006) Advanced computer architectures. CRC Press, Taylor and Francis GroupGoogle Scholar
  5. 5.
    Jadhav SS (2009) Advanced computer architecture and computing. Technical PublicationsGoogle Scholar
  6. 6.
    El-Rewini H, Abd-El-Barr M (2005) Advanced computer architecture and parallel processing. WileyGoogle Scholar
  7. 7.
    Dubois M, Annavaram M, Stenström P (2012) Parallel computer organization and design. Cambridge University PressGoogle Scholar
  8. 8.
    Culler DE, Singh JP, Gupta A (1999) Parallel computer architecture: a hardware/software approach. Morgan KaufmannGoogle Scholar
  9. 9.
    Agrawal DP (1983) Graph theoretical analysis and design of multistage interconnection networks. IEEE Trans Comput 100(7):637–648CrossRefGoogle Scholar
  10. 10.
    Dally WJ, Towles BP (2004) Principles and practices of interconnection networks. Morgan Kaufmann, San Francisco, Calif, USAGoogle Scholar
  11. 11.
    Wang X, Xiang D, Yu Z (2013) TM: a new and simple topology for interconnection networks. J Supercompu 66(1):514–538CrossRefGoogle Scholar
  12. 12.
    Luo W, Xiang D (2012) An efficient adaptive deadlock-free routing algorithm for torus networks. IEEE Trans Parallel Distrib Syst 23(5):800–808CrossRefGoogle Scholar
  13. 13.
    Garofalakis J, Stergiou E (2013) An analytical model for the performance evaluation of multistage interconnection networks with two class priorities. Future Gener Comput Syst 29(1):114–129CrossRefGoogle Scholar
  14. 14.
    Escudero-Sahuquillo J et al (2013) An effective and feasible congestion management technique for high-performance MINs with tag-based distributed routing. IEEE Trans Parallel Distrib Syst 24(10):1918–1929CrossRefGoogle Scholar
  15. 15.
    Swaminathan K, Lakshminarayanan G, Ko S-B (2014) Design and verification of an efficient WISHBONE-based network interface for network on chip. Comput Electri EngCrossRefGoogle Scholar
  16. 16.
    Bistouni F, Jahanshahi M (2014) Improved extra group network: a new fault-tolerant multistage interconnection network. J Supercomput 69(1):161–199CrossRefGoogle Scholar
  17. 17.
    Villar JA et al (2013) An integrated solution for QoS provision and congestion management in high-performance interconnection networks using deterministic source-based routing. J Supercomput 66(1):284–304CrossRefGoogle Scholar
  18. 18.
    Hur JY et al (2007) Systematic customization of on-chip crossbar interconnects. In: Reconfigurable computing: architectures, tools and applications. Springer, Berlin, Heidelberg, pp 61–72Google Scholar
  19. 19.
    Bistouni F, Jahanshahi M (2015) Pars network: a multistage interconnection network with fault-tolerance capability. J Parallel Distrib Comput 75:168–183CrossRefGoogle Scholar
  20. 20.
    Bistouni F, Jahanshahi M (2014) Analyzing the reliability of shuffle-exchange networks using reliability block diagrams. Reliab Eng Syst Safety 132:97–106CrossRefGoogle Scholar
  21. 21.
    Parker DS, Raghavendra CS (1984) The gamma network. IEEE Trans Comput 100(4):367–373CrossRefGoogle Scholar
  22. 22.
    Rajkumar S, Goyal Neeraj Kumar (2014) Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection Networks. J Supercomput 69(1):468–491CrossRefGoogle Scholar
  23. 23.
    Chen C-W, Chung C-P (2005) Designing a disjoint paths interconnection network with fault tolerance and collision solving. J Supercomput 34(1):63–80MathSciNetCrossRefGoogle Scholar
  24. 24.
    Nitin, Garhwal S, Srivastava N (2011) Designing a fault-tolerant fully-chained combining switches multi-stage interconnection network with disjoint paths. J Supercomput 55(3):400–431CrossRefGoogle Scholar
  25. 25.
    Wei S, Lee G (1988) Extra group network: a cost-effective fault-tolerant multistage interconnection network. In: ACM SIGARCH computer architecture news, vol 16. no 2. IEEE Computer Society PressCrossRefGoogle Scholar
  26. 26.
    Matos D et al Hierarchical and multiple switching NoC with floorplan based adaptability. In: Reconfigurable computing: architectures, tools and applications. Springer, Berlin, Heidelberg, pp 179–184Google Scholar
  27. 27.
    Kumar VP, Reddy SM (1987) Augmented shuffle-exchange multistage interconnection networks. Computer 20(6):30–40CrossRefGoogle Scholar
  28. 28.
    Vasiliadis DC, Rizos GE, Vassilakis C (2013) Modelling and performance study of finite-buffered blocking multistage interconnection networks supporting natively 2-class priority routing traffic. J Netw Comput Appl 36(2):723–737CrossRefGoogle Scholar
  29. 29.
    Gunawan I (2008) Reliability analysis of shuffle-exchange network systems. Reliab Eng Syst Safety 93(2):271–276CrossRefGoogle Scholar
  30. 30.
    Blake JT, Trivedi KS (1989) Reliability analysis of interconnection networks using hierarchical composition. IEEE Trans Reliab 38(1):111–120CrossRefGoogle Scholar
  31. 31.
    Bansal PK, Joshi RC, Singh Kuldip (1994) On a fault-tolerant multistage interconnection network. Comput Electr Eng 20(4):335–345CrossRefGoogle Scholar
  32. 32.
    Blake JT, Trivedi KS (1989) Multistage interconnection network reliability. IEEE Trans Comput 38(11):1600–1604CrossRefGoogle Scholar
  33. 33.
    Nitin, Subramanian A (2008) Efficient algorithms and methods to solve dynamic MINs stability problem using stable matching with complete ties. J Discrete Algorithms 6(3):353–380MathSciNetCrossRefGoogle Scholar
  34. 34.
    Fan CCh, Bruck J (2000) Tolerating multiple faults in multistage interconnection networks with minimal extra stages. IEEE Trans Comput 49(9):998–1004CrossRefGoogle Scholar
  35. 35.
    Adams GB, Siegel HJ (1982) The extra stage cube: A fault-tolerant interconnection network for supersystems. IEEE Trans Comput 100(5):443–454CrossRefGoogle Scholar
  36. 36.
    Tutsch D, Hommel G (2008) MLMIN: a multicore processor and parallel computer network topology for multicast. Comput Oper Res 35(12):3807–3821CrossRefGoogle Scholar
  37. 37.
    Çam H (2001) Analysis of Shuffle-Exchange Networks under Permutation Traffic. In: Switching networks: recent advances. Springer US, pp 215–256Google Scholar
  38. 38.
    Çam Hasan (2003) Rearrangeability of (2n-1)-Stage Shuffle-Exchange Networks. SIAM J Comput 32(3):557–585MathSciNetCrossRefGoogle Scholar
  39. 39.
    Dai H, Shen X (2008) Rearrangeability of 7-stage 16 × 16 shuffle exchange networks. Front Electr Electron Eng China 3(4):440–458CrossRefGoogle Scholar
  40. 40.
    Beneš VE (1965) Mathematical theory of connecting networks and telephone traffic. vol 17. Academic PrGoogle Scholar
  41. 41.
    Clos C (1953) A study of non-blocking switching networks. Bell Syst Tech J 32(2):406–424CrossRefGoogle Scholar
  42. 42.
    Kolias C, Tomkos I (2005) Switch fabrics. IEEE Circuits Devices Mag 21(5):12–17CrossRefGoogle Scholar
  43. 43.
    Bistouni F, Jahanshahi M (2015) Scalable crossbar network: a non-blocking interconnection network for large-scale systems. J Supercomput 71(2):697–728CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Computer Engineering, Central Tehran BranchIslamic Azad UniversityTehranIran

Personalised recommendations