Accurate Linearity Testing Using Low-Purity Stimulus Robust against Flicker Noise

  • Yuming Zhuang
  • Degang Chen


Accurately characterizing linearity performance of high-resolution analog-to-digital converters (ADCs) has been a challenging task for many years, since providing input signals whose purity is beyond ADC under test becomes more difficult as the ADC performance becomes better. Previously, the stimulus error identification and removal (SEIR) method used two low-purity ramps with an offset in between. It can achieve accurate linearity test results for a high-precision ADC, but it is vulnerable to flicker noise inherited in the input signals. This chapter proposes two novel methods that eliminate the influence of flicker noise and accurately obtain linearity performance of ADC under test. Using only −40 to −70 dB purity sinusoidal signals, or simple interleaved ramps, the proposed methods are easier to implement and can tolerate the influence of flicker noise while achieving about one least significant bit (LSB) estimation error—the similar level when a pure sinusoidal is used for the same ADC linearity test. The proposed methods are analyzed in detail and comparisons are made between the previous SEIR method. The effectiveness and robustness of the proposed methods against flicker noise are verified through various simulations. The proposed methods help reduce production test cost and simplify the test setup for high-resolution ADC linearity test, suitable for cost-effective on-chip implementation.


  1. 1.
    Y. Zhuang, T. Chen, S. Chaganti, D. Chen, Effect of flicker noise on SEIR for accurate ADC linearity testing, IEEE Int. Midwest. Symp. pp. 1–4, (2015)Google Scholar
  2. 2.
    Y. Zhuang, T. Chen, S. Chaganti, D. Chen, Accurate linearity testing with impure sinusoidal stimulus robust against flicker noise, IEEE VLSI Test Symp. pp. 1–6, Apr. 2016Google Scholar
  3. 3.
    International Technology Roadmap for Semiconductors, (2013),
  4. 4.
    J. Doernberg, H.-S. Lee, D.A. Hodges, Full-speed testing of A/D converters. IEEE J. Solid State Circuits SC-19, 820–827 (1984)CrossRefGoogle Scholar
  5. 5.
    A. van der Ziel, Noise in Solid State Devices and Circuits (Wiley, New York, 1986)Google Scholar
  6. 6.
    IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std.1241, (2010)Google Scholar
  7. 7.
    IEEE Standard for Digitizing Waveform Recorders, IEEE Std.1057, (2007)Google Scholar
  8. 8.
    L. Jin, K. Parthasarathy, T. Kuyel, D. Chen, R. Geiger, Accurate testing of analog-to-digital converters using low linearity signals with stimulus error identification and removal. IEEE Trans. Instrum. Meas. 54(3), 1188–1199 (2005)CrossRefGoogle Scholar
  9. 9.
    L. Jin, D. Chen, R. Geiger, SEIR linearity testing of precision A/D converters in nonstationary environments with center-symmetric interleaving. IEEE Trans. Instrum. Meas. 56(5), 1776–1785 (2007)CrossRefGoogle Scholar
  10. 10.
    X. Dai, C. He, H. Xing, D. Chen, R. Geiger, An N th-order central symmetrical layout pattern for nonlinear gradients cancellation, IEEE Int. Symp. Circuits Syst., pp. 4835–4838, (2005)Google Scholar
  11. 11.
    A.L. McWhorter, 1/f noise and germanium surface properties, in Semiconductor Surface Physics, (University of Pennsylvania Press, Philadelphia, 1957), p. 207Google Scholar
  12. 12.
    F.N. Hooge, L.K.J. Vandamme, Lattice scattering causes 1/f noise. Phys. Lett. 66A, 315 (1978)CrossRefGoogle Scholar
  13. 13.
    K.K. Hung, P.K. Ko, C. Hu, Y.C. Cheng, A unified model for the flicker noise in metal- oxide-semiconductor field-effect transistors. IEEE Trans. on Electron Devices. 37(3), 654–665 (1990)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Yuming Zhuang
    • 1
  • Degang Chen
    • 2
  1. 1.Qualcomm IncSan DiegoUSA
  2. 2.Iowa State UniversityAmesUSA

Personalised recommendations