Skip to main content

Abstract

This chapter summarizes the system models used throughout the book.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 119.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 159.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 159.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Bienia, C., Kumar, S., Singh, J.P., Li, K.: The PARSEC benchmark suite: characterization and architectural implications. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 72–81 (2008)

    Google Scholar 

  2. Kodase, S., Wang, S., Gu, Z., Shin, K.: Improving scalability of task allocation and scheduling in large distributed real-time systems using shared buffers. In: the 9th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 181–188 (2003). https://doi.org/10.1109/RTTAS.2003.1203050

  3. Liu, C.L., Layland, J.W.: Scheduling algorithms for multiprogramming in a hard-real-time environment. J. ACM (JACM) 20(1), 46–61 (1973)

    Article  MathSciNet  Google Scholar 

  4. Yang, C.Y., Chen, J.J., Kuo, T.W.: An approximation algorithm for energy-efficient scheduling on a chip multiprocessor. In: Proceedings of the 8th Design, Automation and Test in Europe (DATE), pp. 468–473 (2005)

    Google Scholar 

  5. Greenhalgh, P.: big.LITTLE processing with ARM Cortex-A15 & Cortex-A7. White paper, ARM Limited (2011)

    Google Scholar 

  6. Binkert, N., Beckmann, B., Black, G., Reinhardt, S.K., Saidi, A., Basu, A., Hestness, J., Hower, D.R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M.D., Wood, D.A.: The gem5 simulator. ACM SIGARCH Comput. Archit. News 39(2), 1–7 (2011)

    Article  Google Scholar 

  7. Li, S., Ahn, J.H., Strong, R., Brockman, J., Tullsen, D., Jouppi, N.: McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In: Proceedings of the 42nd IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 469–480 (2009)

    Google Scholar 

  8. Henkel, J., Khdr, H., Pagani, S., Shafique, M.: New trends in dark silicon. In: Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 119:1–119:6 (2015). https://doi.org/10.1145/2744769.2747938. [HiPEAC Paper Award]

  9. Devadas, V., Aydin, H.: Coordinated power management of periodic real-time tasks on chip multiprocessors. In: Proceedings of the International Conference on Green Computing (GREENCOMP), pp. 61 –72 (2010)

    Google Scholar 

  10. Howard, J., Dighe, S., Vangal, S., Ruhl, G., Borkar, N., Jain, S., Erraguntla, V., Konow, M., Riepen, M., Gries, M., Droege, G., Lund-Larsen, T., Steibl, S., Borkar, S., De, V., Van Der Wijngaart, R.: A 48-core IA-32 processor in 45nm CMOS using on-die message-passing and DVFS for performance and power scaling. IEEE J. Solid-State Circuits 46(1), 173–183 (2011). https://doi.org/10.1109/JSSC.2010.2079450

    Article  Google Scholar 

  11. Chen, J.J., Hsu, H.R., Kuo, T.W.: Leakage-aware energy-efficient scheduling of real-time tasks in multiprocessor systems. DOI https://doi.orgIn: Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 408–417 (2006)

    Google Scholar 

  12. Jejurikar, R., Pereira, C., Gupta, R.: Leakage aware dynamic voltage scaling for real-time embedded systems. In: Proceedings of the 41st IEEE/ACM Design Automation Conference (DAC), pp. 275–280 (2004)

    Google Scholar 

  13. Huang, W., Ghosh, S., Velusamy, S., Sankaranarayanan, K., Skadron, K., Stan, M.: HotSpot: a compact thermal modeling methodology for early-stage VLSI design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(5), 501–513 (2006)

    Article  Google Scholar 

  14. Pagani, S., Khdr, H., Chen, J.J., Shafique, M., Li, M., Henkel, J.: Thermal Safe Power: efficient thermal-aware power budgeting for manycore systems in dark silicon. In: A.M. Rahmani, P. Liljeberg, A. Hemani, A. Jantsch, H. Tenhunen (eds.) The Dark Side of Silicon. Springer (2017)

    Chapter  Google Scholar 

  15. Eguia, T.J.A., Tan, S.X.D., Shen, R., Pacheco, E.H., Tirumala, M.: General behavioral thermal modeling and characterization for multi-core microprocessor design. In: Proceedings of the 18th Design, Automation and Test in Europe (DATE), pp. 1136–1141 (2010)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Santiago Pagani .

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer International Publishing AG, part of Springer Nature

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Pagani, S., Chen, JJ., Shafique, M., Henkel, J. (2018). System Model. In: Advanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores. Springer, Cham. https://doi.org/10.1007/978-3-319-77479-4_3

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-77479-4_3

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-77478-7

  • Online ISBN: 978-3-319-77479-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics